llvm-6502/test/CodeGen/X86/fp-stack-compare-cmov.ll at dc9a217d05eb5b65b51ad1f806166ae6430308b1 - llvm-6502 - Applefritter: Git

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Benjamin Kramer 17c836c4b5 X86: Don't emit conditional floating point moves on when targeting pre-pentiumpro architectures.

* Model FPSW (the FPU status word) as a register.
* Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions.
* During Legalize/Lowering, build a node sequence to transfer the comparison
result from FPSW into EFLAGS. If you're wondering about the right-shift: That's
an implicit sub-register extraction (%ax -> %ah) which is handled later on by
the instruction selector.

Fixes PR6679. Patch by Christoph Erhardt!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155704 91177308-0d34-0410-b5e6-96231b3b80d8

2012-04-27 12:07:43 +00:00

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 ; RUN: llc < %s -march=x86 -mcpu=pentiumpro | FileCheck %s
 ; PR1012
 define float @foo(float* %col.2.0) {
 ; CHECK: fucompi
 ; CHECK: fcmov
   %tmp = load float* %col.2.0
   %tmp16 = fcmp olt float %tmp, 0.000000e+00
   %tmp20 = fsub float -0.000000e+00, %tmp
   %iftmp.2.0 = select i1 %tmp16, float %tmp20, float %tmp
   ret float %iftmp.2.0
 }