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9bdd785014
Some ARM CPUs only support ARM mode (ancient v4 ones, for example) and some only support Thumb mode (M-class ones currently). This makes sure such CPUs default to the correct mode and makes the AsmParser diagnose an attempt to switch modes incorrectly. rdar://14024354 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183710 91177308-0d34-0410-b5e6-96231b3b80d8
34 lines
787 B
ArmAsm
34 lines
787 B
ArmAsm
@ RUN: llvm-mc -triple=armv7-linux-gnueabi -filetype=obj < %s | llvm-objdump -t - | FileCheck %s
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.text
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@ $a at 0x0000
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add r0, r0, r0
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@ $d at 0x0004
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.word 42
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.thumb
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@ $t at 0x0008
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adds r0, r0, r0
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adds r0, r0, r0
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@ $a at 0x000c
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.arm
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add r0, r0, r0
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@ $t at 0x0010
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.thumb
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adds r0, r0, r0
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@ $d at 0x0012
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.ascii "012"
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.byte 1
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.byte 2
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.byte 3
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@ $a at 0x0018
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.arm
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add r0, r0, r0
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@ CHECK: 00000000 .text 00000000 $a
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@ CHECK-NEXT: 0000000c .text 00000000 $a
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@ CHECK-NEXT: 00000018 .text 00000000 $a
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@ CHECK-NEXT: 00000004 .text 00000000 $d
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@ CHECK-NEXT: 00000012 .text 00000000 $d
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@ CHECK-NEXT: 00000008 .text 00000000 $t
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@ CHECK-NEXT: 00000010 .text 00000000 $t
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