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04bcc11905
derived classes. Since global data alignment, layout, and mangling is often based on the DataLayout, move it to the TargetMachine. This ensures that global data is going to be layed out and mangled consistently if the subtarget changes on a per function basis. Prior to this all targets(*) have had subtarget dependent code moved out and onto the TargetMachine. *One target hasn't been migrated as part of this change: R600. The R600 port has, as a subtarget feature, the size of pointers and this affects global data layout. I've currently hacked in a FIXME to enable progress, but the port needs to be updated to either pass the 64-bitness to the TargetMachine, or fix the DataLayout to avoid subtarget dependent features. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227113 91177308-0d34-0410-b5e6-96231b3b80d8
92 lines
2.9 KiB
C++
92 lines
2.9 KiB
C++
//===-- XCoreTargetMachine.cpp - Define TargetMachine for XCore -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "XCoreTargetMachine.h"
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#include "XCoreTargetObjectFile.h"
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#include "XCore.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/Module.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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/// XCoreTargetMachine ctor - Create an ILP32 architecture model
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///
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XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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TLOF(make_unique<XCoreTargetObjectFile>()),
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DL("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32"),
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Subtarget(TT, CPU, FS, *this) {
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initAsmInfo();
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}
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XCoreTargetMachine::~XCoreTargetMachine() {}
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namespace {
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/// XCore Code Generator Pass Configuration Options.
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class XCorePassConfig : public TargetPassConfig {
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public:
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XCorePassConfig(XCoreTargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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XCoreTargetMachine &getXCoreTargetMachine() const {
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return getTM<XCoreTargetMachine>();
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}
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void addIRPasses() override;
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bool addPreISel() override;
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bool addInstSelector() override;
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void addPreEmitPass() override;
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};
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} // namespace
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TargetPassConfig *XCoreTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new XCorePassConfig(this, PM);
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}
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void XCorePassConfig::addIRPasses() {
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addPass(createAtomicExpandPass(&getXCoreTargetMachine()));
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TargetPassConfig::addIRPasses();
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}
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bool XCorePassConfig::addPreISel() {
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addPass(createXCoreLowerThreadLocalPass());
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return false;
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}
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bool XCorePassConfig::addInstSelector() {
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addPass(createXCoreISelDag(getXCoreTargetMachine(), getOptLevel()));
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return false;
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}
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void XCorePassConfig::addPreEmitPass() {
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addPass(createXCoreFrameToArgsOffsetEliminationPass(), false);
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}
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// Force static initialization.
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extern "C" void LLVMInitializeXCoreTarget() {
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RegisterTargetMachine<XCoreTargetMachine> X(TheXCoreTarget);
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}
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void XCoreTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
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// Add first the target-independent BasicTTI pass, then our XCore pass. This
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// allows the XCore pass to delegate to the target independent layer when
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// appropriate.
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PM.add(createBasicTargetTransformInfoPass(this));
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PM.add(createXCoreTargetTransformInfoPass(this));
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}
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