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https://github.com/c64scene-ar/llvm-6502.git
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84f7f350c3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205610 91177308-0d34-0410-b5e6-96231b3b80d8
95 lines
4.0 KiB
C++
95 lines
4.0 KiB
C++
//=== ARM64CallingConv.h - Custom Calling Convention Routines -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the custom routines for the ARM64 Calling Convention that
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// aren't done by tablegen.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARM64CALLINGCONV_H
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#define ARM64CALLINGCONV_H
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#include "ARM64InstrInfo.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/Target/TargetInstrInfo.h"
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namespace llvm {
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/// CC_ARM64_Custom_i1i8i16_Reg - customized handling of passing i1/i8/i16 via
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/// register. Here, ValVT can be i1/i8/i16 or i32 depending on whether the
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/// argument is already promoted and LocVT is i1/i8/i16. We only promote the
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/// argument to i32 if we are sure this argument will be passed in register.
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static bool CC_ARM64_Custom_i1i8i16_Reg(unsigned ValNo, MVT ValVT, MVT LocVT,
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CCValAssign::LocInfo LocInfo,
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ISD::ArgFlagsTy ArgFlags,
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CCState &State,
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bool IsWebKitJS = false) {
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static const MCPhysReg RegList1[] = { ARM64::W0, ARM64::W1, ARM64::W2,
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ARM64::W3, ARM64::W4, ARM64::W5,
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ARM64::W6, ARM64::W7 };
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static const MCPhysReg RegList2[] = { ARM64::X0, ARM64::X1, ARM64::X2,
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ARM64::X3, ARM64::X4, ARM64::X5,
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ARM64::X6, ARM64::X7 };
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static const MCPhysReg WebKitRegList1[] = { ARM64::W0 };
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static const MCPhysReg WebKitRegList2[] = { ARM64::X0 };
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const MCPhysReg *List1 = IsWebKitJS ? WebKitRegList1 : RegList1;
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const MCPhysReg *List2 = IsWebKitJS ? WebKitRegList2 : RegList2;
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if (unsigned Reg = State.AllocateReg(List1, List2, 8)) {
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// Customized extra section for handling i1/i8/i16:
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// We need to promote the argument to i32 if it is not done already.
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if (ValVT != MVT::i32) {
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if (ArgFlags.isSExt())
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LocInfo = CCValAssign::SExt;
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else if (ArgFlags.isZExt())
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LocInfo = CCValAssign::ZExt;
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else
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LocInfo = CCValAssign::AExt;
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ValVT = MVT::i32;
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}
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// Set LocVT to i32 as well if passing via register.
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LocVT = MVT::i32;
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State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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return true;
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}
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return false;
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}
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/// CC_ARM64_WebKit_JS_i1i8i16_Reg - customized handling of passing i1/i8/i16
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/// via register. This behaves the same as CC_ARM64_Custom_i1i8i16_Reg, but only
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/// uses the first register.
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static bool CC_ARM64_WebKit_JS_i1i8i16_Reg(unsigned ValNo, MVT ValVT, MVT LocVT,
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CCValAssign::LocInfo LocInfo,
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ISD::ArgFlagsTy ArgFlags,
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CCState &State) {
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return CC_ARM64_Custom_i1i8i16_Reg(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
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State, true);
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}
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/// CC_ARM64_Custom_i1i8i16_Stack: customized handling of passing i1/i8/i16 on
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/// stack. Here, ValVT can be i1/i8/i16 or i32 depending on whether the argument
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/// is already promoted and LocVT is i1/i8/i16. If ValVT is already promoted,
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/// it will be truncated back to i1/i8/i16.
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static bool CC_ARM64_Custom_i1i8i16_Stack(unsigned ValNo, MVT ValVT, MVT LocVT,
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CCValAssign::LocInfo LocInfo,
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ISD::ArgFlagsTy ArgFlags,
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CCState &State) {
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unsigned Space = ((LocVT == MVT::i1 || LocVT == MVT::i8) ? 1 : 2);
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unsigned Offset12 = State.AllocateStack(Space, Space);
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ValVT = LocVT;
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State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo));
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return true;
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}
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} // End llvm namespace
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#endif
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