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https://github.com/c64scene-ar/llvm-6502.git
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c31891e350
Actually, mostly only those in the top-level directory that already had a "virtual" attached. But it's the thought that counts and it's been a long day. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205131 91177308-0d34-0410-b5e6-96231b3b80d8
70 lines
2.1 KiB
C++
70 lines
2.1 KiB
C++
//===-- ARM64TargetMachine.h - Define TargetMachine for ARM64 ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the ARM64 specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARM64TARGETMACHINE_H
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#define ARM64TARGETMACHINE_H
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#include "ARM64InstrInfo.h"
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#include "ARM64ISelLowering.h"
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#include "ARM64Subtarget.h"
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#include "ARM64FrameLowering.h"
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#include "ARM64SelectionDAGInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/MC/MCStreamer.h"
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namespace llvm {
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class ARM64TargetMachine : public LLVMTargetMachine {
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protected:
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ARM64Subtarget Subtarget;
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private:
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const DataLayout DL;
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ARM64InstrInfo InstrInfo;
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ARM64TargetLowering TLInfo;
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ARM64FrameLowering FrameLowering;
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ARM64SelectionDAGInfo TSInfo;
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public:
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ARM64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
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const TargetOptions &Options, Reloc::Model RM,
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CodeModel::Model CM, CodeGenOpt::Level OL);
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const ARM64Subtarget *getSubtargetImpl() const override { return &Subtarget; }
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const ARM64TargetLowering *getTargetLowering() const override {
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return &TLInfo;
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}
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const DataLayout *getDataLayout() const override { return &DL; }
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const ARM64FrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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}
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const ARM64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
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const ARM64RegisterInfo *getRegisterInfo() const override {
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return &InstrInfo.getRegisterInfo();
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}
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const ARM64SelectionDAGInfo *getSelectionDAGInfo() const override {
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return &TSInfo;
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}
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// Pass Pipeline Configuration
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TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
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/// \brief Register ARM64 analysis passes with a pass manager.
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void addAnalysisPasses(PassManagerBase &PM) override;
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};
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} // end namespace llvm
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#endif
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