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f4c3a5601a
Add implementations of: bool isLegalICmpImmediate(int64_t Imm) const bool isLegalAddImmediate(int64_t Imm) const bool isTruncateFree(Type *Ty1, Type *Ty2) const bool isTruncateFree(EVT VT1, EVT VT2) const bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const Unfortunately, this regresses counter-register-based loop formation because some of the loops now end up in forms were SE cannot compute loop counts. However, nevertheless, the test-suite results favor committing: SingleSource/Benchmarks/BenchmarkGame/puzzle: 26% speedup MultiSource/Benchmarks/FreeBench/analyzer/analyzer: 21% speedup MultiSource/Benchmarks/MiBench/automotive-susan/automotive-susan: 20% speedup SingleSource/Benchmarks/Polybench/linear-algebra/kernels/trisolv/trisolv: 19% speedup SingleSource/Benchmarks/Polybench/linear-algebra/kernels/gesummv/gesummv: 15% speedup MultiSource/Benchmarks/FreeBench/pcompress2/pcompress2: 2% speedup MultiSource/Benchmarks/VersaBench/bmm/bmm: 26% slowdown git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206120 91177308-0d34-0410-b5e6-96231b3b80d8
704 lines
32 KiB
C++
704 lines
32 KiB
C++
//===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that PPC uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
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#define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
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#include "PPC.h"
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#include "PPCInstrInfo.h"
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#include "PPCRegisterInfo.h"
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#include "PPCSubtarget.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLowering.h"
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namespace llvm {
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namespace PPCISD {
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enum NodeType {
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// Start the numbering where the builtin ops and target ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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/// FSEL - Traditional three-operand fsel node.
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///
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FSEL,
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/// FCFID - The FCFID instruction, taking an f64 operand and producing
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/// and f64 value containing the FP representation of the integer that
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/// was temporarily in the f64 operand.
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FCFID,
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/// Newer FCFID[US] integer-to-floating-point conversion instructions for
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/// unsigned integers and single-precision outputs.
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FCFIDU, FCFIDS, FCFIDUS,
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/// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
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/// operand, producing an f64 value containing the integer representation
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/// of that FP value.
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FCTIDZ, FCTIWZ,
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/// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
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/// unsigned integers.
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FCTIDUZ, FCTIWUZ,
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/// Reciprocal estimate instructions (unary FP ops).
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FRE, FRSQRTE,
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// VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
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// three v4f32 operands and producing a v4f32 result.
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VMADDFP, VNMSUBFP,
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/// VPERM - The PPC VPERM Instruction.
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///
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VPERM,
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/// Hi/Lo - These represent the high and low 16-bit parts of a global
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/// address respectively. These nodes have two operands, the first of
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/// which must be a TargetGlobalAddress, and the second of which must be a
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/// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
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/// though these are usually folded into other nodes.
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Hi, Lo,
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TOC_ENTRY,
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/// The following three target-specific nodes are used for calls through
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/// function pointers in the 64-bit SVR4 ABI.
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/// Restore the TOC from the TOC save area of the current stack frame.
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/// This is basically a hard coded load instruction which additionally
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/// takes/produces a flag.
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TOC_RESTORE,
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/// Like a regular LOAD but additionally taking/producing a flag.
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LOAD,
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/// LOAD into r2 (also taking/producing a flag). Like TOC_RESTORE, this is
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/// a hard coded load instruction.
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LOAD_TOC,
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/// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
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/// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
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/// compute an allocation on the stack.
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DYNALLOC,
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/// GlobalBaseReg - On Darwin, this node represents the result of the mflr
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/// at function entry, used for PIC code.
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GlobalBaseReg,
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/// These nodes represent the 32-bit PPC shifts that operate on 6-bit
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/// shift amounts. These nodes are generated by the multi-precision shift
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/// code.
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SRL, SRA, SHL,
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/// CALL - A direct function call.
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/// CALL_NOP is a call with the special NOP which follows 64-bit
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/// SVR4 calls.
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CALL, CALL_NOP,
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/// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
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/// MTCTR instruction.
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MTCTR,
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/// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
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/// BCTRL instruction.
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BCTRL,
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/// Return with a flag operand, matched by 'blr'
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RET_FLAG,
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/// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
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/// This copies the bits corresponding to the specified CRREG into the
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/// resultant GPR. Bits corresponding to other CR regs are undefined.
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MFOCRF,
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// FIXME: Remove these once the ANDI glue bug is fixed:
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/// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
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/// eq or gt bit of CR0 after executing andi. x, 1. This is used to
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/// implement truncation of i32 or i64 to i1.
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ANDIo_1_EQ_BIT, ANDIo_1_GT_BIT,
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// EH_SJLJ_SETJMP - SjLj exception handling setjmp.
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EH_SJLJ_SETJMP,
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// EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
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EH_SJLJ_LONGJMP,
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/// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
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/// instructions. For lack of better number, we use the opcode number
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/// encoding for the OPC field to identify the compare. For example, 838
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/// is VCMPGTSH.
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VCMP,
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/// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
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/// altivec VCMP*o instructions. For lack of better number, we use the
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/// opcode number encoding for the OPC field to identify the compare. For
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/// example, 838 is VCMPGTSH.
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VCMPo,
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/// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
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/// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
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/// condition register to branch on, OPC is the branch opcode to use (e.g.
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/// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
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/// an optional input flag argument.
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COND_BRANCH,
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/// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
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/// loops.
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BDNZ, BDZ,
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/// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
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/// towards zero. Used only as part of the long double-to-int
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/// conversion sequence.
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FADDRTZ,
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/// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
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MFFS,
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/// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
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/// reserve indexed. This is used to implement atomic operations.
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LARX,
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/// STCX = This corresponds to PPC stcx. instrcution: store conditional
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/// indexed. This is used to implement atomic operations.
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STCX,
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/// TC_RETURN - A tail call return.
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/// operand #0 chain
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/// operand #1 callee (register or absolute)
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/// operand #2 stack adjustment
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/// operand #3 optional in flag
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TC_RETURN,
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/// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
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CR6SET,
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CR6UNSET,
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/// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
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/// on PPC32.
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PPC32_GOT,
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/// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec
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/// TLS model, produces an ADDIS8 instruction that adds the GOT
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/// base to sym\@got\@tprel\@ha.
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ADDIS_GOT_TPREL_HA,
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/// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
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/// TLS model, produces a LD instruction with base register G8RReg
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/// and offset sym\@got\@tprel\@l. This completes the addition that
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/// finds the offset of "sym" relative to the thread pointer.
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LD_GOT_TPREL_L,
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/// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
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/// model, produces an ADD instruction that adds the contents of
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/// G8RReg to the thread pointer. Symbol contains a relocation
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/// sym\@tls which is to be replaced by the thread pointer and
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/// identifies to the linker that the instruction is part of a
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/// TLS sequence.
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ADD_TLS,
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/// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS
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/// model, produces an ADDIS8 instruction that adds the GOT base
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/// register to sym\@got\@tlsgd\@ha.
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ADDIS_TLSGD_HA,
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/// G8RC = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
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/// model, produces an ADDI8 instruction that adds G8RReg to
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/// sym\@got\@tlsgd\@l.
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ADDI_TLSGD_L,
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/// G8RC = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS
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/// model, produces a call to __tls_get_addr(sym\@tlsgd).
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GET_TLS_ADDR,
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/// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS
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/// model, produces an ADDIS8 instruction that adds the GOT base
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/// register to sym\@got\@tlsld\@ha.
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ADDIS_TLSLD_HA,
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/// G8RC = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
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/// model, produces an ADDI8 instruction that adds G8RReg to
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/// sym\@got\@tlsld\@l.
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ADDI_TLSLD_L,
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/// G8RC = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS
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/// model, produces a call to __tls_get_addr(sym\@tlsld).
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GET_TLSLD_ADDR,
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/// G8RC = ADDIS_DTPREL_HA %X3, Symbol, Chain - For the
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/// local-dynamic TLS model, produces an ADDIS8 instruction
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/// that adds X3 to sym\@dtprel\@ha. The Chain operand is needed
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/// to tie this in place following a copy to %X3 from the result
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/// of a GET_TLSLD_ADDR.
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ADDIS_DTPREL_HA,
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/// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
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/// model, produces an ADDI8 instruction that adds G8RReg to
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/// sym\@got\@dtprel\@l.
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ADDI_DTPREL_L,
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/// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
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/// during instruction selection to optimize a BUILD_VECTOR into
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/// operations on splats. This is necessary to avoid losing these
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/// optimizations due to constant folding.
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VADD_SPLAT,
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/// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned
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/// operand identifies the operating system entry point.
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SC,
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/// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
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/// byte-swapping store instruction. It byte-swaps the low "Type" bits of
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/// the GPRC input, then stores it through Ptr. Type can be either i16 or
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/// i32.
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STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
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/// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
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/// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
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/// then puts it in the bottom bits of the GPRC. TYPE can be either i16
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/// or i32.
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LBRX,
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/// STFIWX - The STFIWX instruction. The first operand is an input token
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/// chain, then an f64 value to store, then an address to store it to.
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STFIWX,
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/// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
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/// load which sign-extends from a 32-bit integer value into the
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/// destination 64-bit register.
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LFIWAX,
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/// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
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/// load which zero-extends from a 32-bit integer value into the
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/// destination 64-bit register.
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LFIWZX,
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/// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium and large code model,
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/// produces an ADDIS8 instruction that adds the TOC base register to
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/// sym\@toc\@ha.
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ADDIS_TOC_HA,
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/// G8RC = LD_TOC_L Symbol, G8RReg - For medium and large code model,
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/// produces a LD instruction with base register G8RReg and offset
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/// sym\@toc\@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
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LD_TOC_L,
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/// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces
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/// an ADDI8 instruction that adds G8RReg to sym\@toc\@l.
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/// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
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ADDI_TOC_L
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};
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}
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/// Define some predicates that are used for node matching.
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namespace PPC {
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/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
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/// VPKUHUM instruction.
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bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
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/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
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/// VPKUWUM instruction.
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bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
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/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
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/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
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bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
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bool isUnary);
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/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
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/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
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bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
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bool isUnary);
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/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
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/// amount, otherwise return -1.
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int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
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/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a splat of a single element that is suitable for input to
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/// VSPLTB/VSPLTH/VSPLTW.
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bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
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/// isAllNegativeZeroVector - Returns true if all elements of build_vector
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/// are -0.0.
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bool isAllNegativeZeroVector(SDNode *N);
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/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
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/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
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unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
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/// get_VSPLTI_elt - If this is a build_vector of constants which can be
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/// formed by using a vspltis[bhw] instruction of the specified element
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/// size, return the constant being splatted. The ByteSize field indicates
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/// the number of bytes of each element [124] -> [bhw].
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SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
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}
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class PPCTargetLowering : public TargetLowering {
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const PPCSubtarget &PPCSubTarget;
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public:
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explicit PPCTargetLowering(PPCTargetMachine &TM);
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/// getTargetNodeName() - This method returns the name of a target specific
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/// DAG node.
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
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/// getSetCCResultType - Return the ISD::SETCC ValueType
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virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
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/// getPreIndexedAddressParts - returns true by value, base pointer and
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/// offset pointer and addressing mode by reference if the node's address
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/// can be legally represented as pre-indexed load / store address.
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virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
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SDValue &Offset,
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ISD::MemIndexedMode &AM,
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SelectionDAG &DAG) const;
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/// SelectAddressRegReg - Given the specified addressed, check to see if it
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/// can be represented as an indexed [r+r] operation. Returns false if it
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/// can be more efficiently represented with [r+imm].
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bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
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SelectionDAG &DAG) const;
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/// SelectAddressRegImm - Returns true if the address N can be represented
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/// by a base register plus a signed 16-bit displacement [r+imm], and if it
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/// is not better represented as reg+reg. If Aligned is true, only accept
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/// displacements suitable for STD and friends, i.e. multiples of 4.
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bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
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SelectionDAG &DAG, bool Aligned) const;
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/// SelectAddressRegRegOnly - Given the specified addressed, force it to be
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/// represented as an indexed [r+r] operation.
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bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
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SelectionDAG &DAG) const;
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Sched::Preference getSchedulingPreference(SDNode *N) const;
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/// LowerOperation - Provide custom lowering hooks for some operations.
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///
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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/// ReplaceNodeResults - Replace the results of node with an illegal result
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/// type with new values built out of custom code.
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///
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virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
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SelectionDAG &DAG) const;
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virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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virtual void computeMaskedBitsForTargetNode(const SDValue Op,
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APInt &KnownZero,
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APInt &KnownOne,
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const SelectionDAG &DAG,
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unsigned Depth = 0) const;
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virtual MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
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MachineBasicBlock *MBB, bool is64Bit,
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unsigned BinOpcode) const;
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MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
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MachineBasicBlock *MBB,
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bool is8bit, unsigned Opcode) const;
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MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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ConstraintType getConstraintType(const std::string &Constraint) const;
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/// Examine constraint string and operand type and determine a weight value.
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/// The operand object must already have been set up with the operand type.
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ConstraintWeight getSingleConstraintMatchWeight(
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|
AsmOperandInfo &info, const char *constraint) const;
|
|
|
|
std::pair<unsigned, const TargetRegisterClass*>
|
|
getRegForInlineAsmConstraint(const std::string &Constraint,
|
|
MVT VT) const;
|
|
|
|
/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
|
|
/// function arguments in the caller parameter area. This is the actual
|
|
/// alignment, not its logarithm.
|
|
unsigned getByValTypeAlignment(Type *Ty) const;
|
|
|
|
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
|
|
/// vector. If it is invalid, don't add anything to Ops.
|
|
virtual void LowerAsmOperandForConstraint(SDValue Op,
|
|
std::string &Constraint,
|
|
std::vector<SDValue> &Ops,
|
|
SelectionDAG &DAG) const;
|
|
|
|
/// isLegalAddressingMode - Return true if the addressing mode represented
|
|
/// by AM is legal for this target, for a load/store of the specified type.
|
|
virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
|
|
|
|
/// isLegalICmpImmediate - Return true if the specified immediate is legal
|
|
/// icmp immediate, that is the target has icmp instructions which can
|
|
/// compare a register against the immediate without having to materialize
|
|
/// the immediate into a register.
|
|
bool isLegalICmpImmediate(int64_t Imm) const override;
|
|
|
|
/// isLegalAddImmediate - Return true if the specified immediate is legal
|
|
/// add immediate, that is the target has add instructions which can
|
|
/// add a register and the immediate without having to materialize
|
|
/// the immediate into a register.
|
|
bool isLegalAddImmediate(int64_t Imm) const override;
|
|
|
|
/// isTruncateFree - Return true if it's free to truncate a value of
|
|
/// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in
|
|
/// register X1 to i32 by referencing its sub-register R1.
|
|
bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
|
|
bool isTruncateFree(EVT VT1, EVT VT2) const override;
|
|
|
|
/// \brief Returns true if it is beneficial to convert a load of a constant
|
|
/// to just the constant itself.
|
|
bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
|
|
Type *Ty) const override;
|
|
|
|
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
|
|
|
|
/// getOptimalMemOpType - Returns the target specific optimal type for load
|
|
/// and store operations as a result of memset, memcpy, and memmove
|
|
/// lowering. If DstAlign is zero that means it's safe to destination
|
|
/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
|
|
/// means there isn't a need to check it against alignment requirement,
|
|
/// probably because the source does not need to be loaded. If 'IsMemset' is
|
|
/// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
|
|
/// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
|
|
/// source is constant so it does not need to be loaded.
|
|
/// It returns EVT::Other if the type should be determined using generic
|
|
/// target-independent logic.
|
|
virtual EVT
|
|
getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
|
|
bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
|
|
MachineFunction &MF) const;
|
|
|
|
/// Is unaligned memory access allowed for the given type, and is it fast
|
|
/// relative to software emulation.
|
|
virtual bool allowsUnalignedMemoryAccesses(EVT VT,
|
|
unsigned AddrSpace,
|
|
bool *Fast = 0) const;
|
|
|
|
/// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
|
|
/// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
|
|
/// expanded to FMAs when this method returns true, otherwise fmuladd is
|
|
/// expanded to fmul + fadd.
|
|
virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const;
|
|
|
|
// Should we expand the build vector with shuffles?
|
|
virtual bool
|
|
shouldExpandBuildVectorWithShuffles(EVT VT,
|
|
unsigned DefinedValues) const;
|
|
|
|
/// createFastISel - This method returns a target-specific FastISel object,
|
|
/// or null if the target does not support "fast" instruction selection.
|
|
virtual FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
|
|
const TargetLibraryInfo *LibInfo) const;
|
|
|
|
private:
|
|
SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
|
|
SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
|
|
|
|
bool
|
|
IsEligibleForTailCallOptimization(SDValue Callee,
|
|
CallingConv::ID CalleeCC,
|
|
bool isVarArg,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
SelectionDAG& DAG) const;
|
|
|
|
SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
|
|
int SPDiff,
|
|
SDValue Chain,
|
|
SDValue &LROpOut,
|
|
SDValue &FPOpOut,
|
|
bool isDarwinABI,
|
|
SDLoc dl) const;
|
|
|
|
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
|
|
const PPCSubtarget &Subtarget) const;
|
|
SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
|
|
const PPCSubtarget &Subtarget) const;
|
|
SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG,
|
|
const PPCSubtarget &Subtarget) const;
|
|
SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
|
|
const PPCSubtarget &Subtarget) const;
|
|
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
|
|
const PPCSubtarget &Subtarget) const;
|
|
SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDLoc dl) const;
|
|
SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
SDLoc dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
|
SDValue FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall,
|
|
bool isVarArg,
|
|
SelectionDAG &DAG,
|
|
SmallVector<std::pair<unsigned, SDValue>, 8>
|
|
&RegsToPass,
|
|
SDValue InFlag, SDValue Chain,
|
|
SDValue &Callee,
|
|
int SPDiff, unsigned NumBytes,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
|
|
|
virtual SDValue
|
|
LowerFormalArguments(SDValue Chain,
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
SDLoc dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
|
|
|
virtual SDValue
|
|
LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
|
|
|
virtual bool
|
|
CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
|
|
bool isVarArg,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
LLVMContext &Context) const;
|
|
|
|
virtual SDValue
|
|
LowerReturn(SDValue Chain,
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
|
SDLoc dl, SelectionDAG &DAG) const;
|
|
|
|
SDValue
|
|
extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG,
|
|
SDValue ArgVal, SDLoc dl) const;
|
|
|
|
void
|
|
setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
|
|
unsigned nAltivecParamsAtEnd,
|
|
unsigned MinReservedArea, bool isPPC64) const;
|
|
|
|
SDValue
|
|
LowerFormalArguments_Darwin(SDValue Chain,
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
SDLoc dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
|
SDValue
|
|
LowerFormalArguments_64SVR4(SDValue Chain,
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
SDLoc dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
|
SDValue
|
|
LowerFormalArguments_32SVR4(SDValue Chain,
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
SDLoc dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
|
|
|
SDValue
|
|
createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
|
|
SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
|
|
SelectionDAG &DAG, SDLoc dl) const;
|
|
|
|
SDValue
|
|
LowerCall_Darwin(SDValue Chain, SDValue Callee,
|
|
CallingConv::ID CallConv,
|
|
bool isVarArg, bool isTailCall,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
SDLoc dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
|
SDValue
|
|
LowerCall_64SVR4(SDValue Chain, SDValue Callee,
|
|
CallingConv::ID CallConv,
|
|
bool isVarArg, bool isTailCall,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
SDLoc dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
|
SDValue
|
|
LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
|
|
bool isVarArg, bool isTailCall,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
SDLoc dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
|
|
|
SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
SDValue DAGCombineFastRecip(SDValue Op, DAGCombinerInfo &DCI) const;
|
|
SDValue DAGCombineFastRecipFSQRT(SDValue Op, DAGCombinerInfo &DCI) const;
|
|
|
|
CCAssignFn *useFastISelCCs(unsigned Flag) const;
|
|
};
|
|
|
|
namespace PPC {
|
|
FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
|
|
const TargetLibraryInfo *LibInfo);
|
|
}
|
|
|
|
bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
|
|
CCValAssign::LocInfo &LocInfo,
|
|
ISD::ArgFlagsTy &ArgFlags,
|
|
CCState &State);
|
|
|
|
bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
|
|
MVT &LocVT,
|
|
CCValAssign::LocInfo &LocInfo,
|
|
ISD::ArgFlagsTy &ArgFlags,
|
|
CCState &State);
|
|
|
|
bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
|
|
MVT &LocVT,
|
|
CCValAssign::LocInfo &LocInfo,
|
|
ISD::ArgFlagsTy &ArgFlags,
|
|
CCState &State);
|
|
}
|
|
|
|
#endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
|