Andrew Trick de0847d6a5 Hide the pre-RA-sched= option. ...

This is a very confusing option for a feature that will go away.

-enable-misched is exposed instead to help triage issues with the new
scheduler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199133 91177308-0d34-0410-b5e6-96231b3b80d8

2014-01-13 20:08:27 +00:00

..

Analysis

[PM] Split DominatorTree into a concrete analysis result object which

2014-01-13 13:07:17 +00:00

AsmParser

Move the LLVM IR asm writer header files into the IR directory, as they

2014-01-07 12:34:26 +00:00

Bitcode

Update getLazyBitcodeModule to use ErrorOr for error handling.

2014-01-13 18:31:04 +00:00

CodeGen

Hide the pre-RA-sched= option.

2014-01-13 20:08:27 +00:00

DebugInfo

llvm-dwarfdump: type unit dwo support

2014-01-09 05:08:24 +00:00

ExecutionEngine

Re-sort #include lines again, prior to moving headers around.

2014-01-13 08:04:33 +00:00

IR

[PM] Split DominatorTree into a concrete analysis result object which

2014-01-13 13:07:17 +00:00

IRReader

Update getLazyBitcodeModule to use ErrorOr for error handling.

2014-01-13 18:31:04 +00:00

Linker

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LTO

Update getLazyBitcodeModule to use ErrorOr for error handling.

2014-01-13 18:31:04 +00:00

MC

Fix indentation.

2014-01-13 15:50:36 +00:00

Object

Re-sort all of the includes with ./utils/sort_includes.py so that

2014-01-07 11:48:04 +00:00

Option

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Support

raw_fd_ostream: Don't change STDERR to O_BINARY, or w*printf() (in assert()) would barf wide chars after llvm::errs().

2014-01-12 16:14:24 +00:00

TableGen

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Target

Fix PR 18369: [Thumbv8] asserts due to inconsistent CPSR liveness of IT blocks

2014-01-13 18:47:54 +00:00

Transforms

[PM] Split DominatorTree into a concrete analysis result object which

2014-01-13 13:07:17 +00:00

CMakeLists.txt

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LLVMBuild.txt

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Makefile

…