Rafael Espindola de2b854310 Fix warning in non-assert build. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182443 91177308-0d34-0410-b5e6-96231b3b80d8

2013-05-22 01:29:38 +00:00

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InstPrinter

R600: Improve texture handling

2013-05-17 16:50:20 +00:00

MCTargetDesc

Fix the build in c++11 mode.

2013-05-17 22:45:52 +00:00

TargetInfo

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AMDGPU.h

R600: Improve texture handling

2013-05-17 16:50:20 +00:00

AMDGPU.td

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AMDGPUAsmPrinter.cpp

R600: Emit config values in register / value pairs

2013-05-06 17:50:51 +00:00

AMDGPUAsmPrinter.h

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AMDGPUCallingConv.td

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AMDGPUConvertToISA.cpp

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AMDGPUFrameLowering.cpp

…

AMDGPUFrameLowering.h

…

AMDGPUIndirectAddressing.cpp

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AMDGPUInstrInfo.cpp

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AMDGPUInstrInfo.h

…

AMDGPUInstrInfo.td

R600: Swap the legality of rotl and rotr

2013-05-20 15:02:19 +00:00

AMDGPUInstructions.td

R600: Swap the legality of rotl and rotr

2013-05-20 15:02:19 +00:00

AMDGPUIntrinsics.td

…

AMDGPUISelLowering.cpp

R600: Swap the legality of rotl and rotr

2013-05-20 15:02:19 +00:00

AMDGPUISelLowering.h

R600: Swap the legality of rotl and rotr

2013-05-20 15:02:19 +00:00

AMDGPUMachineFunction.cpp

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AMDGPUMachineFunction.h

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AMDGPUMCInstLower.cpp

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AMDGPUMCInstLower.h

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AMDGPURegisterInfo.cpp

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AMDGPURegisterInfo.h

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AMDGPURegisterInfo.td

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AMDGPUStructurizeCFG.cpp

…

AMDGPUSubtarget.cpp

R600: Factorize Fetch size limit inside AMDGPUSubTarget

2013-05-17 16:49:55 +00:00

AMDGPUSubtarget.h

R600: Factorize Fetch size limit inside AMDGPUSubTarget

2013-05-17 16:49:55 +00:00

AMDGPUTargetMachine.cpp

R600: Improve texture handling

2013-05-17 16:50:20 +00:00

AMDGPUTargetMachine.h

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AMDIL7XXDevice.cpp

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AMDIL7XXDevice.h

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AMDIL.h

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AMDILBase.td

R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions

2013-04-30 00:13:39 +00:00

AMDILCFGStructurizer.cpp

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AMDILDevice.cpp

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AMDILDevice.h

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AMDILDeviceInfo.cpp

R600/SI: Add processor type for Hainan asic

2013-05-14 14:42:56 +00:00

AMDILDeviceInfo.h

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AMDILDevices.h

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AMDILEvergreenDevice.cpp

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AMDILEvergreenDevice.h

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AMDILInstrInfo.td

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AMDILIntrinsicInfo.cpp

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AMDILIntrinsicInfo.h

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AMDILIntrinsics.td

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AMDILISelDAGToDAG.cpp

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AMDILISelLowering.cpp

R600: Swap the legality of rotl and rotr

2013-05-20 15:02:19 +00:00

AMDILNIDevice.cpp

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AMDILNIDevice.h

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AMDILRegisterInfo.td

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AMDILSIDevice.cpp

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AMDILSIDevice.h

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CMakeLists.txt

R600: Improve texture handling

2013-05-17 16:50:20 +00:00

LLVMBuild.txt

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Makefile

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Processors.td

R600/SI: Add processor type for Hainan asic

2013-05-14 14:42:56 +00:00

R600ControlFlowFinalizer.cpp

R600: Some factorization

2013-05-17 16:50:02 +00:00

R600Defines.h

R600: Relax some vector constraints on Dot4.

2013-05-17 16:50:32 +00:00

R600EmitClauseMarkers.cpp

R600: Relax some vector constraints on Dot4.

2013-05-17 16:50:32 +00:00

R600ExpandSpecialInstrs.cpp

Fix warning in non-assert build.

2013-05-22 01:29:38 +00:00

R600InstrInfo.cpp

R600: Relax some vector constraints on Dot4.

2013-05-17 16:50:32 +00:00

R600InstrInfo.h

R600: Relax some vector constraints on Dot4.

2013-05-17 16:50:32 +00:00

R600Instructions.td

R600: Swap the legality of rotl and rotr

2013-05-20 15:02:19 +00:00

R600Intrinsics.td

R600: Improve texture handling

2013-05-17 16:50:20 +00:00

R600ISelLowering.cpp

R600: Swap the legality of rotl and rotr

2013-05-20 15:02:19 +00:00

R600ISelLowering.h

Add LLVMContext argument to getSetCCResultType

2013-05-18 00:21:46 +00:00

R600MachineFunctionInfo.cpp

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R600MachineFunctionInfo.h

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R600MachineScheduler.cpp

R600: Use bottom up scheduling algorithm

2013-05-17 16:50:56 +00:00

R600MachineScheduler.h

R600: Use bottom up scheduling algorithm

2013-05-17 16:50:56 +00:00

R600Packetizer.cpp

R600: Relax some vector constraints on Dot4.

2013-05-17 16:50:32 +00:00

R600RegisterInfo.cpp

R600: Use bottom up scheduling algorithm

2013-05-17 16:50:56 +00:00

R600RegisterInfo.h

R600: Use bottom up scheduling algorithm

2013-05-17 16:50:56 +00:00

R600RegisterInfo.td

R600: Rename 128 bit registers.

2013-05-17 16:50:09 +00:00

R600Schedule.td

R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips

2013-04-30 00:14:17 +00:00

R600TextureIntrinsicsReplacer.cpp

R600: Fix bug detected by GCC warning.

2013-05-20 15:58:43 +00:00

SIAnnotateControlFlow.cpp

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SIDefines.h

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SIInsertWaits.cpp

…

SIInstrFormats.td

R600/SI: Use the same names for VOP3 operands and encoding fields

2013-05-20 15:02:08 +00:00

SIInstrInfo.cpp

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SIInstrInfo.h

…

SIInstrInfo.td

R600/SI: Use a multiclass for MUBUF_Load_Helper

2013-05-20 15:02:31 +00:00

SIInstructions.td

R600/SI: Use a multiclass for MUBUF_Load_Helper

2013-05-20 15:02:31 +00:00

SIIntrinsics.td

R600/SI: Add intrinsic for MIMG IMAGE_GET_RESINFO opcode

2013-05-06 23:02:19 +00:00

SIISelLowering.cpp

R600/SI: Make fitsRegClass() operands const

2013-05-20 15:02:01 +00:00

SIISelLowering.h

R600/SI: Make fitsRegClass() operands const

2013-05-20 15:02:01 +00:00

SILowerControlFlow.cpp

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SIMachineFunctionInfo.cpp

…

SIMachineFunctionInfo.h

…

SIRegisterInfo.cpp

…

SIRegisterInfo.h

…

SIRegisterInfo.td

…

SISchedule.td

…