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llvm-6502/test/CodeGen/Mips
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Akira Hatanaka 97d9f081a9 Implement MipsTargetLowering::CanLowerReturn. 
Patch by Sasa Stankovic. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165585 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 01:27:09 +00:00
..
2008-06-05-Carry.ll
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2008-07-03-SRet.ll
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2008-07-06-fadd64.ll
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2008-07-07-Float2Int.ll
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2008-07-07-FPExtend.ll
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2008-07-07-IntDoubleConvertions.ll
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2008-07-15-InternalConstant.ll
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2008-07-15-SmallSection.ll
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2008-07-16-SignExtInReg.ll
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2008-07-22-Cstpool.ll
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2008-07-23-fpcmp.ll
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2008-07-29-icmp.ll
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2008-07-31-fcopysign.ll
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2008-08-01-AsmInline.ll
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2008-08-03-fabs64.ll
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2008-08-03-ReturnDouble.ll
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2008-08-04-Bitconvert.ll
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2008-08-06-Alloca.ll
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2008-08-07-CC.ll
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2008-08-07-FPRound.ll
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2008-08-08-bswap.ll
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2008-08-08-ctlz.ll
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2008-10-13-LegalizerBug.ll
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2008-11-10-xint_to_fp.ll
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2009-11-16-CstPoolLoad.ll
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2010-04-07-DbgValueOtherTargets.ll
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2010-07-20-Switch.ll
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2010-11-09-CountLeading.ll
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2010-11-09-Mul.ll
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2011-05-26-BranchKillsVreg.ll
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addc.ll
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alloca.ll
Expand DYNAMIC_STACKALLOC nodes rather than doing custom-lowering.
2012-07-31 20:54:48 +00:00
analyzebranch.ll
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and1.ll
1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
2012-08-03 22:57:02 +00:00
asm-large-immediate.ll
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atomic.ll
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blockaddr.ll
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br-jmp.ll
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brdelayslot.ll
Disable Mips' delay slot filler when optimization level is O0.
2012-08-24 20:40:15 +00:00
bswap.ll
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buildpairextractelementf64.ll
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cmov.ll
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constantfp0.ll
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cprestore.ll
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divrem.ll
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double2int.ll
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dsp-r1.ll
MIPS DSP: add operands to make sure instruction strings are being matched.
2012-09-28 21:23:16 +00:00
dsp-r2.ll
MIPS DSP: add operands to make sure instruction strings are being matched.
2012-09-28 21:23:16 +00:00
eh.ll
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extins.ll
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fabs.ll
Add test triples to fix win32 failures. Revert workaround from r161292.
2012-08-08 20:31:37 +00:00
fastcc.ll
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fcopysign-f32-f64.ll
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fcopysign.ll
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fmadd1.ll
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fneg.ll
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fp-indexed-ls.ll
Fix type of LUXC1 and SUXC1. These instructions were incorrectly defined as
2012-07-31 18:16:49 +00:00
fp-spill-reload.ll
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fpbr.ll
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frame-address.ll
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frem.ll
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global-address.ll
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global-pointer-reg.ll
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gprestore.ll
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helloworld.ll
When store nodes or memcpy nodes are created to copy the function call
2012-07-31 18:46:41 +00:00
i64arg.ll
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imm.ll
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indirectcall.ll
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init-array.ll
Fix UseInitArray option for MIPS target.
2012-09-05 06:17:17 +00:00
inlineasm64.ll
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inlineasm_constraint.ll
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inlineasm-cnstrnt-bad-I-1.ll
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inlineasm-cnstrnt-bad-J.ll
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inlineasm-cnstrnt-bad-K.ll
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inlineasm-cnstrnt-bad-L.ll
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inlineasm-cnstrnt-bad-N.ll
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inlineasm-cnstrnt-bad-O.ll
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inlineasm-cnstrnt-bad-P.ll
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inlineasm-cnstrnt-reg64.ll
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inlineasm-cnstrnt-reg.ll
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inlineasm-operand-code.ll
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inlineasmmemop.ll
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internalfunc.ll
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largeimm1.ll
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largeimmprinting.ll
Add definitions of two subclasses of MipsFrameLowering, Mips16FrameLowering and
2012-07-31 22:50:19 +00:00
lb1.ll
1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
2012-08-03 22:57:02 +00:00
lbu1.ll
1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
2012-08-03 22:57:02 +00:00
lh1.ll
1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
2012-08-03 22:57:02 +00:00
lhu1.ll
1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
2012-08-03 22:57:02 +00:00
lit.local.cfg
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load-store-left-right.ll
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longbranch.ll
Fix mips' long branch pass.
2012-08-28 03:03:05 +00:00
machineverifier.ll
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madd-msub.ll
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memcpy.ll
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mips64-fp-indexed-ls.ll
Fix type of LUXC1 and SUXC1. These instructions were incorrectly defined as
2012-07-31 18:16:49 +00:00
mips64countleading.ll
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mips64directive.ll
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mips64ext.ll
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mips64extins.ll
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mips64fpimm0.ll
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mips64fpldst.ll
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mips64imm.ll
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mips64instrs.ll
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mips64intldst.ll
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mips64lea.ll
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mips64load-store-left-right.ll
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mips64muldiv.ll
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mips64shift.ll
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mipslopat.ll
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mul.ll
Patch for integer multiply, signed/unsigned, long/long long.
2012-10-05 18:27:54 +00:00
mulll.ll
Patch for integer multiply, signed/unsigned, long/long long.
2012-10-05 18:27:54 +00:00
mulull.ll
Patch for integer multiply, signed/unsigned, long/long long.
2012-10-05 18:27:54 +00:00
neg1.ll
1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
2012-08-03 22:57:02 +00:00
not1.ll
1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
2012-08-03 22:57:02 +00:00
null.ll
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o32_cc_byval.ll
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o32_cc_vararg.ll
Set transient stack alignment in constructor of MipsFrameLowering and re-enable
2012-08-02 18:15:13 +00:00
o32_cc.ll
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or1.ll
1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
2012-08-03 22:57:02 +00:00
private.ll
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ra-allocatable.ll
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rdhwr-directives.ll
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return_address.ll
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return-vector-float4.ll
Test case for r162008.
2012-08-16 03:48:41 +00:00
return-vector.ll
Implement MipsTargetLowering::CanLowerReturn.
2012-10-10 01:27:09 +00:00
rotate.ll
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sb1.ll
1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
2012-08-03 22:57:02 +00:00
select.ll
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selectcc.ll
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sh1.ll
1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
2012-08-03 22:57:02 +00:00
shift-parts.ll
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sitofp-selectcc-opt.ll
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sll1.ll
1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
2012-08-03 22:57:02 +00:00
sll2.ll
1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
2012-08-03 22:57:02 +00:00
small-section-reserve-gp.ll
In MipsDAGToDAGISel::SelectAddr, fold add node into address operand, if its
2012-08-24 20:21:49 +00:00
sra1.ll
1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
2012-08-03 22:57:02 +00:00
sra2.ll
1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
2012-08-03 22:57:02 +00:00
srl1.ll
1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
2012-08-03 22:57:02 +00:00
srl2.ll
1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
2012-08-03 22:57:02 +00:00
stacksize.ll
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stldst.ll
checking test case for r164811. was an omission to not check this in. this was already approved
2012-10-01 21:35:06 +00:00
sub1.ll
1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
2012-08-03 22:57:02 +00:00
sub2.ll
1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
2012-08-03 22:57:02 +00:00
swzero.ll
Don't modify MO while use_iterator is still pointing to it.
2012-08-09 22:08:24 +00:00
tls-alias.ll
Add option disable-mips-delay-filler. Turn on mips' delay slot filler by
2012-08-22 02:51:28 +00:00
tls-models.ll
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tls.ll
Add option disable-mips-delay-filler. Turn on mips' delay slot filler by
2012-08-22 02:51:28 +00:00
uitofp.ll
Fix bug 13532.
2012-08-28 02:12:42 +00:00
ul1.ll
Handled unaligned load/stores properly in Mips16
2012-09-15 01:02:03 +00:00
unalignedload.ll
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vector-load-store.ll
MIPS DSP: add vector load/store patterns.
2012-09-27 01:50:59 +00:00
weak.ll
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xor1.ll
1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
2012-08-03 22:57:02 +00:00
zeroreg.ll
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