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e1820a6a4e
Summary: This is a white lie to workaround a widespread bug in the -mfp64 implementation. The problem is that none of the 32-bit fpu ops mention the fact that they clobber the upper 32-bits of the 64-bit FPR. This allows MFHC1 to be scheduled on the wrong side of most 32-bit FPU ops. Fixing that requires a major overhaul of the FPU implementation which can't be done right now due to time constraints. MFHC1 is one of two affected instructions. These instructions are the only FPU instructions that don't read or write the lower 32-bits. We therefore pretend that it reads the bottom 32-bits to artificially create a dependency and prevent the scheduler changing the behaviour of the code. The other instruction is MTHC1 which will be fixed once I've have found a failing test case for it. The testcase is test-suite/SingleSource/UnitTests/Vector/simple.c when given TARGET_CFLAGS="-mips32r2 -mfp64 -mmsa". Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2966 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203464 91177308-0d34-0410-b5e6-96231b3b80d8
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