llvm-6502/lib/Target/Hexagon
Jyotsna Verma 55a98b00c1 Hexagon: Set appropriate TSFlags to the loads/stores with global address to
support constant extension.

This patch doesn't introduce any functionality changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175280 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15 17:52:07 +00:00
..
InstPrinter
MCTargetDesc
TargetInfo
CMakeLists.txt Extend Hexagon hardware loop generation to handle various additional cases: 2013-02-11 21:37:55 +00:00
Hexagon.h Hexagon: Use absolute addressing mode loads/stores for global+offset 2013-02-13 21:38:46 +00:00
Hexagon.td
HexagonAsmPrinter.cpp
HexagonAsmPrinter.h
HexagonCallingConv.td
HexagonCallingConvLower.cpp
HexagonCallingConvLower.h
HexagonCFGOptimizer.cpp
HexagonExpandPredSpillCode.cpp
HexagonFixupHwLoops.cpp Extend Hexagon hardware loop generation to handle various additional cases: 2013-02-11 21:37:55 +00:00
HexagonFrameLowering.cpp
HexagonFrameLowering.h
HexagonHardwareLoops.cpp Extend Hexagon hardware loop generation to handle various additional cases: 2013-02-11 21:37:55 +00:00
HexagonInstrFormats.td Hexagon: Change insn class to support instruction encoding. 2013-02-14 19:57:17 +00:00
HexagonInstrFormatsV4.td Hexagon: Change insn class to support instruction encoding. 2013-02-14 19:57:17 +00:00
HexagonInstrInfo.cpp Hexagon: add support for predicate-GPR copies. 2013-02-13 22:56:34 +00:00
HexagonInstrInfo.h
HexagonInstrInfo.td Hexagon: Change insn class to support instruction encoding. 2013-02-14 19:57:17 +00:00
HexagonInstrInfoV3.td
HexagonInstrInfoV4.td Hexagon: Set appropriate TSFlags to the loads/stores with global address to 2013-02-15 17:52:07 +00:00
HexagonInstrInfoV5.td
HexagonIntrinsics.td
HexagonIntrinsicsDerived.td
HexagonIntrinsicsV3.td
HexagonIntrinsicsV4.td
HexagonIntrinsicsV5.td
HexagonISelDAGToDAG.cpp Hexagon: Use absolute addressing mode loads/stores for global+offset 2013-02-13 21:38:46 +00:00
HexagonISelLowering.cpp
HexagonISelLowering.h
HexagonMachineFunctionInfo.h
HexagonMachineScheduler.cpp MIsched: HazardRecognizers are created for each DAG. Free them. 2013-02-13 19:22:27 +00:00
HexagonMachineScheduler.h
HexagonMCInst.h
HexagonMCInstLower.cpp
HexagonNewValueJump.cpp
HexagonOperands.td
HexagonPeephole.cpp
HexagonRegisterInfo.cpp
HexagonRegisterInfo.h
HexagonRegisterInfo.td
HexagonRemoveSZExtArgs.cpp
HexagonSchedule.td Hexagon: Change insn class to support instruction encoding. 2013-02-14 19:57:17 +00:00
HexagonScheduleV4.td Hexagon: Change insn class to support instruction encoding. 2013-02-14 19:57:17 +00:00
HexagonSelectCCInfo.td
HexagonSelectionDAGInfo.cpp
HexagonSelectionDAGInfo.h
HexagonSplitTFRCondSets.cpp
HexagonSubtarget.cpp
HexagonSubtarget.h
HexagonTargetMachine.cpp Hexagon: Use absolute addressing mode loads/stores for global+offset 2013-02-13 21:38:46 +00:00
HexagonTargetMachine.h
HexagonTargetObjectFile.cpp
HexagonTargetObjectFile.h
HexagonVarargsCallingConvention.h
HexagonVLIWPacketizer.cpp Hexagon: Use absolute addressing mode loads/stores for global+offset 2013-02-13 21:38:46 +00:00
LLVMBuild.txt
Makefile