mirror of
https://github.com/c64scene-ar/llvm-6502.git
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943ce55f39
This reverts commit r200058 and adds the using directive for ARMTargetTransformInfo to silence two g++ overload warnings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200062 91177308-0d34-0410-b5e6-96231b3b80d8
792 lines
28 KiB
C++
792 lines
28 KiB
C++
//===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements a TargetTransformInfo analysis pass specific to the
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/// X86 target machine. It uses the target's detailed information to provide
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/// more precise answers to certain TTI queries, while letting the target
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/// independent and default TTI implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "x86tti"
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#include "X86.h"
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#include "X86TargetMachine.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/IR/IntrinsicInst.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/CostTable.h"
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#include "llvm/Target/TargetLowering.h"
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using namespace llvm;
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// Declare the pass initialization routine locally as target-specific passes
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// don't havve a target-wide initialization entry point, and so we rely on the
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// pass constructor initialization.
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namespace llvm {
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void initializeX86TTIPass(PassRegistry &);
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}
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namespace {
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class X86TTI LLVM_FINAL : public ImmutablePass, public TargetTransformInfo {
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const X86Subtarget *ST;
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const X86TargetLowering *TLI;
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/// Estimate the overhead of scalarizing an instruction. Insert and Extract
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/// are set if the result needs to be inserted and/or extracted from vectors.
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unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
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public:
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X86TTI() : ImmutablePass(ID), ST(0), TLI(0) {
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llvm_unreachable("This pass cannot be directly constructed");
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}
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X86TTI(const X86TargetMachine *TM)
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: ImmutablePass(ID), ST(TM->getSubtargetImpl()),
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TLI(TM->getTargetLowering()) {
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initializeX86TTIPass(*PassRegistry::getPassRegistry());
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}
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virtual void initializePass() LLVM_OVERRIDE {
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pushTTIStack(this);
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}
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virtual void finalizePass() {
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popTTIStack();
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}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const LLVM_OVERRIDE {
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TargetTransformInfo::getAnalysisUsage(AU);
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}
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/// Pass identification.
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static char ID;
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/// Provide necessary pointer adjustments for the two base classes.
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virtual void *getAdjustedAnalysisPointer(const void *ID) LLVM_OVERRIDE {
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if (ID == &TargetTransformInfo::ID)
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return (TargetTransformInfo*)this;
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return this;
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}
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/// \name Scalar TTI Implementations
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/// @{
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virtual PopcntSupportKind
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getPopcntSupport(unsigned TyWidth) const LLVM_OVERRIDE;
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/// @}
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/// \name Vector TTI Implementations
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/// @{
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virtual unsigned getNumberOfRegisters(bool Vector) const LLVM_OVERRIDE;
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virtual unsigned getRegisterBitWidth(bool Vector) const LLVM_OVERRIDE;
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virtual unsigned getMaximumUnrollFactor() const LLVM_OVERRIDE;
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virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
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OperandValueKind,
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OperandValueKind) const LLVM_OVERRIDE;
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virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
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int Index, Type *SubTp) const LLVM_OVERRIDE;
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virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
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Type *Src) const LLVM_OVERRIDE;
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virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
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Type *CondTy) const LLVM_OVERRIDE;
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virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
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unsigned Index) const LLVM_OVERRIDE;
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virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
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unsigned Alignment,
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unsigned AddressSpace) const LLVM_OVERRIDE;
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virtual unsigned
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getAddressComputationCost(Type *PtrTy, bool IsComplex) const LLVM_OVERRIDE;
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virtual unsigned getReductionCost(unsigned Opcode, Type *Ty,
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bool IsPairwiseForm) const LLVM_OVERRIDE;
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virtual unsigned getIntImmCost(const APInt &Imm,
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Type *Ty) const LLVM_OVERRIDE;
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virtual unsigned getIntImmCost(unsigned Opcode, const APInt &Imm,
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Type *Ty) const LLVM_OVERRIDE;
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virtual unsigned getIntImmCost(Intrinsic::ID IID, const APInt &Imm,
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Type *Ty) const LLVM_OVERRIDE;
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/// @}
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};
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} // end anonymous namespace
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INITIALIZE_AG_PASS(X86TTI, TargetTransformInfo, "x86tti",
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"X86 Target Transform Info", true, true, false)
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char X86TTI::ID = 0;
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ImmutablePass *
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llvm::createX86TargetTransformInfoPass(const X86TargetMachine *TM) {
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return new X86TTI(TM);
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}
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//===----------------------------------------------------------------------===//
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//
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// X86 cost model.
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//
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//===----------------------------------------------------------------------===//
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X86TTI::PopcntSupportKind X86TTI::getPopcntSupport(unsigned TyWidth) const {
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assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
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// TODO: Currently the __builtin_popcount() implementation using SSE3
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// instructions is inefficient. Once the problem is fixed, we should
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// call ST->hasSSE3() instead of ST->hasPOPCNT().
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return ST->hasPOPCNT() ? PSK_FastHardware : PSK_Software;
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}
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unsigned X86TTI::getNumberOfRegisters(bool Vector) const {
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if (Vector && !ST->hasSSE1())
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return 0;
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if (ST->is64Bit())
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return 16;
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return 8;
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}
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unsigned X86TTI::getRegisterBitWidth(bool Vector) const {
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if (Vector) {
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if (ST->hasAVX()) return 256;
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if (ST->hasSSE1()) return 128;
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return 0;
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}
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if (ST->is64Bit())
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return 64;
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return 32;
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}
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unsigned X86TTI::getMaximumUnrollFactor() const {
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if (ST->isAtom())
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return 1;
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// Sandybridge and Haswell have multiple execution ports and pipelined
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// vector units.
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if (ST->hasAVX())
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return 4;
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return 2;
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}
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unsigned X86TTI::getArithmeticInstrCost(unsigned Opcode, Type *Ty,
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OperandValueKind Op1Info,
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OperandValueKind Op2Info) const {
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// Legalize the type.
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std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Ty);
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int ISD = TLI->InstructionOpcodeToISD(Opcode);
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assert(ISD && "Invalid opcode");
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static const CostTblEntry<MVT::SimpleValueType> AVX2CostTable[] = {
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// Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to
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// customize them to detect the cases where shift amount is a scalar one.
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{ ISD::SHL, MVT::v4i32, 1 },
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{ ISD::SRL, MVT::v4i32, 1 },
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{ ISD::SRA, MVT::v4i32, 1 },
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{ ISD::SHL, MVT::v8i32, 1 },
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{ ISD::SRL, MVT::v8i32, 1 },
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{ ISD::SRA, MVT::v8i32, 1 },
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{ ISD::SHL, MVT::v2i64, 1 },
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{ ISD::SRL, MVT::v2i64, 1 },
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{ ISD::SHL, MVT::v4i64, 1 },
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{ ISD::SRL, MVT::v4i64, 1 },
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{ ISD::SHL, MVT::v32i8, 42 }, // cmpeqb sequence.
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{ ISD::SHL, MVT::v16i16, 16*10 }, // Scalarized.
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{ ISD::SRL, MVT::v32i8, 32*10 }, // Scalarized.
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{ ISD::SRL, MVT::v16i16, 8*10 }, // Scalarized.
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{ ISD::SRA, MVT::v32i8, 32*10 }, // Scalarized.
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{ ISD::SRA, MVT::v16i16, 16*10 }, // Scalarized.
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{ ISD::SRA, MVT::v4i64, 4*10 }, // Scalarized.
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// Vectorizing division is a bad idea. See the SSE2 table for more comments.
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{ ISD::SDIV, MVT::v32i8, 32*20 },
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{ ISD::SDIV, MVT::v16i16, 16*20 },
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{ ISD::SDIV, MVT::v8i32, 8*20 },
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{ ISD::SDIV, MVT::v4i64, 4*20 },
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{ ISD::UDIV, MVT::v32i8, 32*20 },
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{ ISD::UDIV, MVT::v16i16, 16*20 },
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{ ISD::UDIV, MVT::v8i32, 8*20 },
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{ ISD::UDIV, MVT::v4i64, 4*20 },
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};
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// Look for AVX2 lowering tricks.
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if (ST->hasAVX2()) {
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int Idx = CostTableLookup(AVX2CostTable, ISD, LT.second);
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if (Idx != -1)
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return LT.first * AVX2CostTable[Idx].Cost;
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}
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static const CostTblEntry<MVT::SimpleValueType>
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SSE2UniformConstCostTable[] = {
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// We don't correctly identify costs of casts because they are marked as
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// custom.
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// Constant splats are cheaper for the following instructions.
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{ ISD::SHL, MVT::v16i8, 1 }, // psllw.
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{ ISD::SHL, MVT::v8i16, 1 }, // psllw.
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{ ISD::SHL, MVT::v4i32, 1 }, // pslld
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{ ISD::SHL, MVT::v2i64, 1 }, // psllq.
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{ ISD::SRL, MVT::v16i8, 1 }, // psrlw.
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{ ISD::SRL, MVT::v8i16, 1 }, // psrlw.
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{ ISD::SRL, MVT::v4i32, 1 }, // psrld.
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{ ISD::SRL, MVT::v2i64, 1 }, // psrlq.
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{ ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb.
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{ ISD::SRA, MVT::v8i16, 1 }, // psraw.
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{ ISD::SRA, MVT::v4i32, 1 }, // psrad.
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};
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if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
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ST->hasSSE2()) {
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int Idx = CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second);
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if (Idx != -1)
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return LT.first * SSE2UniformConstCostTable[Idx].Cost;
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}
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static const CostTblEntry<MVT::SimpleValueType> SSE2CostTable[] = {
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// We don't correctly identify costs of casts because they are marked as
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// custom.
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// For some cases, where the shift amount is a scalar we would be able
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// to generate better code. Unfortunately, when this is the case the value
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// (the splat) will get hoisted out of the loop, thereby making it invisible
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// to ISel. The cost model must return worst case assumptions because it is
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// used for vectorization and we don't want to make vectorized code worse
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// than scalar code.
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{ ISD::SHL, MVT::v16i8, 30 }, // cmpeqb sequence.
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{ ISD::SHL, MVT::v8i16, 8*10 }, // Scalarized.
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{ ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul.
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{ ISD::SHL, MVT::v2i64, 2*10 }, // Scalarized.
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{ ISD::SRL, MVT::v16i8, 16*10 }, // Scalarized.
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{ ISD::SRL, MVT::v8i16, 8*10 }, // Scalarized.
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{ ISD::SRL, MVT::v4i32, 4*10 }, // Scalarized.
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{ ISD::SRL, MVT::v2i64, 2*10 }, // Scalarized.
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{ ISD::SRA, MVT::v16i8, 16*10 }, // Scalarized.
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{ ISD::SRA, MVT::v8i16, 8*10 }, // Scalarized.
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{ ISD::SRA, MVT::v4i32, 4*10 }, // Scalarized.
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{ ISD::SRA, MVT::v2i64, 2*10 }, // Scalarized.
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// It is not a good idea to vectorize division. We have to scalarize it and
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// in the process we will often end up having to spilling regular
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// registers. The overhead of division is going to dominate most kernels
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// anyways so try hard to prevent vectorization of division - it is
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// generally a bad idea. Assume somewhat arbitrarily that we have to be able
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// to hide "20 cycles" for each lane.
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{ ISD::SDIV, MVT::v16i8, 16*20 },
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{ ISD::SDIV, MVT::v8i16, 8*20 },
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{ ISD::SDIV, MVT::v4i32, 4*20 },
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{ ISD::SDIV, MVT::v2i64, 2*20 },
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{ ISD::UDIV, MVT::v16i8, 16*20 },
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{ ISD::UDIV, MVT::v8i16, 8*20 },
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{ ISD::UDIV, MVT::v4i32, 4*20 },
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{ ISD::UDIV, MVT::v2i64, 2*20 },
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};
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if (ST->hasSSE2()) {
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int Idx = CostTableLookup(SSE2CostTable, ISD, LT.second);
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if (Idx != -1)
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return LT.first * SSE2CostTable[Idx].Cost;
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}
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static const CostTblEntry<MVT::SimpleValueType> AVX1CostTable[] = {
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// We don't have to scalarize unsupported ops. We can issue two half-sized
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// operations and we only need to extract the upper YMM half.
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// Two ops + 1 extract + 1 insert = 4.
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{ ISD::MUL, MVT::v8i32, 4 },
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{ ISD::SUB, MVT::v8i32, 4 },
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{ ISD::ADD, MVT::v8i32, 4 },
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{ ISD::SUB, MVT::v4i64, 4 },
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{ ISD::ADD, MVT::v4i64, 4 },
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// A v4i64 multiply is custom lowered as two split v2i64 vectors that then
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// are lowered as a series of long multiplies(3), shifts(4) and adds(2)
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// Because we believe v4i64 to be a legal type, we must also include the
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// split factor of two in the cost table. Therefore, the cost here is 18
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// instead of 9.
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{ ISD::MUL, MVT::v4i64, 18 },
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};
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// Look for AVX1 lowering tricks.
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if (ST->hasAVX() && !ST->hasAVX2()) {
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int Idx = CostTableLookup(AVX1CostTable, ISD, LT.second);
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if (Idx != -1)
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return LT.first * AVX1CostTable[Idx].Cost;
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}
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// Custom lowering of vectors.
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static const CostTblEntry<MVT::SimpleValueType> CustomLowered[] = {
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// A v2i64/v4i64 and multiply is custom lowered as a series of long
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// multiplies(3), shifts(4) and adds(2).
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{ ISD::MUL, MVT::v2i64, 9 },
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{ ISD::MUL, MVT::v4i64, 9 },
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};
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int Idx = CostTableLookup(CustomLowered, ISD, LT.second);
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if (Idx != -1)
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return LT.first * CustomLowered[Idx].Cost;
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// Special lowering of v4i32 mul on sse2, sse3: Lower v4i32 mul as 2x shuffle,
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// 2x pmuludq, 2x shuffle.
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if (ISD == ISD::MUL && LT.second == MVT::v4i32 && ST->hasSSE2() &&
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!ST->hasSSE41())
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return 6;
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// Fallback to the default implementation.
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return TargetTransformInfo::getArithmeticInstrCost(Opcode, Ty, Op1Info,
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Op2Info);
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}
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unsigned X86TTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
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Type *SubTp) const {
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// We only estimate the cost of reverse shuffles.
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if (Kind != SK_Reverse)
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return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
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std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp);
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unsigned Cost = 1;
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if (LT.second.getSizeInBits() > 128)
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Cost = 3; // Extract + insert + copy.
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// Multiple by the number of parts.
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return Cost * LT.first;
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}
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unsigned X86TTI::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const {
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int ISD = TLI->InstructionOpcodeToISD(Opcode);
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assert(ISD && "Invalid opcode");
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std::pair<unsigned, MVT> LTSrc = TLI->getTypeLegalizationCost(Src);
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std::pair<unsigned, MVT> LTDest = TLI->getTypeLegalizationCost(Dst);
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static const TypeConversionCostTblEntry<MVT::SimpleValueType>
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SSE2ConvTbl[] = {
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// These are somewhat magic numbers justified by looking at the output of
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// Intel's IACA, running some kernels and making sure when we take
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// legalization into account the throughput will be overestimated.
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
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{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
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{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
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{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
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{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
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// There are faster sequences for float conversions.
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{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
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{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 },
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{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
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{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
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{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
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{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 },
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{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
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{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
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};
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if (ST->hasSSE2() && !ST->hasAVX()) {
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int Idx =
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ConvertCostTableLookup(SSE2ConvTbl, ISD, LTDest.second, LTSrc.second);
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if (Idx != -1)
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return LTSrc.first * SSE2ConvTbl[Idx].Cost;
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}
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EVT SrcTy = TLI->getValueType(Src);
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EVT DstTy = TLI->getValueType(Dst);
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// The function getSimpleVT only handles simple value types.
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if (!SrcTy.isSimple() || !DstTy.isSimple())
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return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
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static const TypeConversionCostTblEntry<MVT::SimpleValueType>
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AVXConversionTbl[] = {
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{ ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
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{ ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
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{ ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
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{ ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
|
|
{ ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
|
|
{ ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
|
|
{ ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 },
|
|
{ ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 1 },
|
|
{ ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 },
|
|
|
|
{ ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 },
|
|
{ ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 },
|
|
{ ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
|
|
{ ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 },
|
|
{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
|
|
{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
|
|
{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 },
|
|
{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
|
|
{ ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 },
|
|
{ ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 },
|
|
{ ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 },
|
|
{ ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 },
|
|
|
|
{ ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 },
|
|
{ ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 },
|
|
{ ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
|
|
{ ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 },
|
|
{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 },
|
|
{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 },
|
|
{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
|
|
{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 },
|
|
{ ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 },
|
|
{ ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 },
|
|
{ ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 },
|
|
{ ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 },
|
|
|
|
{ ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 1 },
|
|
{ ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
|
|
{ ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 6 },
|
|
{ ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 9 },
|
|
{ ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 8 },
|
|
{ ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 },
|
|
{ ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 },
|
|
{ ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 },
|
|
};
|
|
|
|
if (ST->hasAVX()) {
|
|
int Idx = ConvertCostTableLookup(AVXConversionTbl, ISD, DstTy.getSimpleVT(),
|
|
SrcTy.getSimpleVT());
|
|
if (Idx != -1)
|
|
return AVXConversionTbl[Idx].Cost;
|
|
}
|
|
|
|
return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
|
|
}
|
|
|
|
unsigned X86TTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
|
|
Type *CondTy) const {
|
|
// Legalize the type.
|
|
std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy);
|
|
|
|
MVT MTy = LT.second;
|
|
|
|
int ISD = TLI->InstructionOpcodeToISD(Opcode);
|
|
assert(ISD && "Invalid opcode");
|
|
|
|
static const CostTblEntry<MVT::SimpleValueType> SSE42CostTbl[] = {
|
|
{ ISD::SETCC, MVT::v2f64, 1 },
|
|
{ ISD::SETCC, MVT::v4f32, 1 },
|
|
{ ISD::SETCC, MVT::v2i64, 1 },
|
|
{ ISD::SETCC, MVT::v4i32, 1 },
|
|
{ ISD::SETCC, MVT::v8i16, 1 },
|
|
{ ISD::SETCC, MVT::v16i8, 1 },
|
|
};
|
|
|
|
static const CostTblEntry<MVT::SimpleValueType> AVX1CostTbl[] = {
|
|
{ ISD::SETCC, MVT::v4f64, 1 },
|
|
{ ISD::SETCC, MVT::v8f32, 1 },
|
|
// AVX1 does not support 8-wide integer compare.
|
|
{ ISD::SETCC, MVT::v4i64, 4 },
|
|
{ ISD::SETCC, MVT::v8i32, 4 },
|
|
{ ISD::SETCC, MVT::v16i16, 4 },
|
|
{ ISD::SETCC, MVT::v32i8, 4 },
|
|
};
|
|
|
|
static const CostTblEntry<MVT::SimpleValueType> AVX2CostTbl[] = {
|
|
{ ISD::SETCC, MVT::v4i64, 1 },
|
|
{ ISD::SETCC, MVT::v8i32, 1 },
|
|
{ ISD::SETCC, MVT::v16i16, 1 },
|
|
{ ISD::SETCC, MVT::v32i8, 1 },
|
|
};
|
|
|
|
if (ST->hasAVX2()) {
|
|
int Idx = CostTableLookup(AVX2CostTbl, ISD, MTy);
|
|
if (Idx != -1)
|
|
return LT.first * AVX2CostTbl[Idx].Cost;
|
|
}
|
|
|
|
if (ST->hasAVX()) {
|
|
int Idx = CostTableLookup(AVX1CostTbl, ISD, MTy);
|
|
if (Idx != -1)
|
|
return LT.first * AVX1CostTbl[Idx].Cost;
|
|
}
|
|
|
|
if (ST->hasSSE42()) {
|
|
int Idx = CostTableLookup(SSE42CostTbl, ISD, MTy);
|
|
if (Idx != -1)
|
|
return LT.first * SSE42CostTbl[Idx].Cost;
|
|
}
|
|
|
|
return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy);
|
|
}
|
|
|
|
unsigned X86TTI::getVectorInstrCost(unsigned Opcode, Type *Val,
|
|
unsigned Index) const {
|
|
assert(Val->isVectorTy() && "This must be a vector type");
|
|
|
|
if (Index != -1U) {
|
|
// Legalize the type.
|
|
std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Val);
|
|
|
|
// This type is legalized to a scalar type.
|
|
if (!LT.second.isVector())
|
|
return 0;
|
|
|
|
// The type may be split. Normalize the index to the new type.
|
|
unsigned Width = LT.second.getVectorNumElements();
|
|
Index = Index % Width;
|
|
|
|
// Floating point scalars are already located in index #0.
|
|
if (Val->getScalarType()->isFloatingPointTy() && Index == 0)
|
|
return 0;
|
|
}
|
|
|
|
return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
|
|
}
|
|
|
|
unsigned X86TTI::getScalarizationOverhead(Type *Ty, bool Insert,
|
|
bool Extract) const {
|
|
assert (Ty->isVectorTy() && "Can only scalarize vectors");
|
|
unsigned Cost = 0;
|
|
|
|
for (int i = 0, e = Ty->getVectorNumElements(); i < e; ++i) {
|
|
if (Insert)
|
|
Cost += TopTTI->getVectorInstrCost(Instruction::InsertElement, Ty, i);
|
|
if (Extract)
|
|
Cost += TopTTI->getVectorInstrCost(Instruction::ExtractElement, Ty, i);
|
|
}
|
|
|
|
return Cost;
|
|
}
|
|
|
|
unsigned X86TTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
|
|
unsigned AddressSpace) const {
|
|
// Handle non-power-of-two vectors such as <3 x float>
|
|
if (VectorType *VTy = dyn_cast<VectorType>(Src)) {
|
|
unsigned NumElem = VTy->getVectorNumElements();
|
|
|
|
// Handle a few common cases:
|
|
// <3 x float>
|
|
if (NumElem == 3 && VTy->getScalarSizeInBits() == 32)
|
|
// Cost = 64 bit store + extract + 32 bit store.
|
|
return 3;
|
|
|
|
// <3 x double>
|
|
if (NumElem == 3 && VTy->getScalarSizeInBits() == 64)
|
|
// Cost = 128 bit store + unpack + 64 bit store.
|
|
return 3;
|
|
|
|
// Assume that all other non-power-of-two numbers are scalarized.
|
|
if (!isPowerOf2_32(NumElem)) {
|
|
unsigned Cost = TargetTransformInfo::getMemoryOpCost(Opcode,
|
|
VTy->getScalarType(),
|
|
Alignment,
|
|
AddressSpace);
|
|
unsigned SplitCost = getScalarizationOverhead(Src,
|
|
Opcode == Instruction::Load,
|
|
Opcode==Instruction::Store);
|
|
return NumElem * Cost + SplitCost;
|
|
}
|
|
}
|
|
|
|
// Legalize the type.
|
|
std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
|
|
assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
|
|
"Invalid Opcode");
|
|
|
|
// Each load/store unit costs 1.
|
|
unsigned Cost = LT.first * 1;
|
|
|
|
// On Sandybridge 256bit load/stores are double pumped
|
|
// (but not on Haswell).
|
|
if (LT.second.getSizeInBits() > 128 && !ST->hasAVX2())
|
|
Cost*=2;
|
|
|
|
return Cost;
|
|
}
|
|
|
|
unsigned X86TTI::getAddressComputationCost(Type *Ty, bool IsComplex) const {
|
|
// Address computations in vectorized code with non-consecutive addresses will
|
|
// likely result in more instructions compared to scalar code where the
|
|
// computation can more often be merged into the index mode. The resulting
|
|
// extra micro-ops can significantly decrease throughput.
|
|
unsigned NumVectorInstToHideOverhead = 10;
|
|
|
|
if (Ty->isVectorTy() && IsComplex)
|
|
return NumVectorInstToHideOverhead;
|
|
|
|
return TargetTransformInfo::getAddressComputationCost(Ty, IsComplex);
|
|
}
|
|
|
|
unsigned X86TTI::getReductionCost(unsigned Opcode, Type *ValTy,
|
|
bool IsPairwise) const {
|
|
|
|
std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy);
|
|
|
|
MVT MTy = LT.second;
|
|
|
|
int ISD = TLI->InstructionOpcodeToISD(Opcode);
|
|
assert(ISD && "Invalid opcode");
|
|
|
|
// We use the Intel Architecture Code Analyzer(IACA) to measure the throughput
|
|
// and make it as the cost.
|
|
|
|
static const CostTblEntry<MVT::SimpleValueType> SSE42CostTblPairWise[] = {
|
|
{ ISD::FADD, MVT::v2f64, 2 },
|
|
{ ISD::FADD, MVT::v4f32, 4 },
|
|
{ ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6".
|
|
{ ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5".
|
|
{ ISD::ADD, MVT::v8i16, 5 },
|
|
};
|
|
|
|
static const CostTblEntry<MVT::SimpleValueType> AVX1CostTblPairWise[] = {
|
|
{ ISD::FADD, MVT::v4f32, 4 },
|
|
{ ISD::FADD, MVT::v4f64, 5 },
|
|
{ ISD::FADD, MVT::v8f32, 7 },
|
|
{ ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5".
|
|
{ ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5".
|
|
{ ISD::ADD, MVT::v4i64, 5 }, // The data reported by the IACA tool is "4.8".
|
|
{ ISD::ADD, MVT::v8i16, 5 },
|
|
{ ISD::ADD, MVT::v8i32, 5 },
|
|
};
|
|
|
|
static const CostTblEntry<MVT::SimpleValueType> SSE42CostTblNoPairWise[] = {
|
|
{ ISD::FADD, MVT::v2f64, 2 },
|
|
{ ISD::FADD, MVT::v4f32, 4 },
|
|
{ ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6".
|
|
{ ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3".
|
|
{ ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3".
|
|
};
|
|
|
|
static const CostTblEntry<MVT::SimpleValueType> AVX1CostTblNoPairWise[] = {
|
|
{ ISD::FADD, MVT::v4f32, 3 },
|
|
{ ISD::FADD, MVT::v4f64, 3 },
|
|
{ ISD::FADD, MVT::v8f32, 4 },
|
|
{ ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5".
|
|
{ ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "2.8".
|
|
{ ISD::ADD, MVT::v4i64, 3 },
|
|
{ ISD::ADD, MVT::v8i16, 4 },
|
|
{ ISD::ADD, MVT::v8i32, 5 },
|
|
};
|
|
|
|
if (IsPairwise) {
|
|
if (ST->hasAVX()) {
|
|
int Idx = CostTableLookup(AVX1CostTblPairWise, ISD, MTy);
|
|
if (Idx != -1)
|
|
return LT.first * AVX1CostTblPairWise[Idx].Cost;
|
|
}
|
|
|
|
if (ST->hasSSE42()) {
|
|
int Idx = CostTableLookup(SSE42CostTblPairWise, ISD, MTy);
|
|
if (Idx != -1)
|
|
return LT.first * SSE42CostTblPairWise[Idx].Cost;
|
|
}
|
|
} else {
|
|
if (ST->hasAVX()) {
|
|
int Idx = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy);
|
|
if (Idx != -1)
|
|
return LT.first * AVX1CostTblNoPairWise[Idx].Cost;
|
|
}
|
|
|
|
if (ST->hasSSE42()) {
|
|
int Idx = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy);
|
|
if (Idx != -1)
|
|
return LT.first * SSE42CostTblNoPairWise[Idx].Cost;
|
|
}
|
|
}
|
|
|
|
return TargetTransformInfo::getReductionCost(Opcode, ValTy, IsPairwise);
|
|
}
|
|
|
|
unsigned X86TTI::getIntImmCost(const APInt &Imm, Type *Ty) const {
|
|
assert(Ty->isIntegerTy());
|
|
|
|
unsigned BitSize = Ty->getPrimitiveSizeInBits();
|
|
if (BitSize == 0)
|
|
return ~0U;
|
|
|
|
if (Imm.getBitWidth() <= 64 &&
|
|
(isInt<32>(Imm.getSExtValue()) || isUInt<32>(Imm.getZExtValue())))
|
|
return TCC_Basic;
|
|
else
|
|
return 2 * TCC_Basic;
|
|
}
|
|
|
|
unsigned X86TTI::getIntImmCost(unsigned Opcode, const APInt &Imm,
|
|
Type *Ty) const {
|
|
assert(Ty->isIntegerTy());
|
|
|
|
unsigned BitSize = Ty->getPrimitiveSizeInBits();
|
|
if (BitSize == 0)
|
|
return ~0U;
|
|
|
|
switch (Opcode) {
|
|
case Instruction::Add:
|
|
case Instruction::Sub:
|
|
case Instruction::Mul:
|
|
case Instruction::UDiv:
|
|
case Instruction::SDiv:
|
|
case Instruction::URem:
|
|
case Instruction::SRem:
|
|
case Instruction::Shl:
|
|
case Instruction::LShr:
|
|
case Instruction::AShr:
|
|
case Instruction::And:
|
|
case Instruction::Or:
|
|
case Instruction::Xor:
|
|
case Instruction::ICmp:
|
|
if (Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue()))
|
|
return TCC_Free;
|
|
else
|
|
return X86TTI::getIntImmCost(Imm, Ty);
|
|
case Instruction::Trunc:
|
|
case Instruction::ZExt:
|
|
case Instruction::SExt:
|
|
case Instruction::IntToPtr:
|
|
case Instruction::PtrToInt:
|
|
case Instruction::BitCast:
|
|
case Instruction::Call:
|
|
case Instruction::Select:
|
|
case Instruction::Ret:
|
|
case Instruction::Load:
|
|
case Instruction::Store:
|
|
return X86TTI::getIntImmCost(Imm, Ty);
|
|
}
|
|
return TargetTransformInfo::getIntImmCost(Opcode, Imm, Ty);
|
|
}
|
|
|
|
unsigned X86TTI::getIntImmCost(Intrinsic::ID IID, const APInt &Imm,
|
|
Type *Ty) const {
|
|
assert(Ty->isIntegerTy());
|
|
|
|
unsigned BitSize = Ty->getPrimitiveSizeInBits();
|
|
if (BitSize == 0)
|
|
return ~0U;
|
|
|
|
switch (IID) {
|
|
default: return TargetTransformInfo::getIntImmCost(IID, Imm, Ty);
|
|
case Intrinsic::sadd_with_overflow:
|
|
case Intrinsic::uadd_with_overflow:
|
|
case Intrinsic::ssub_with_overflow:
|
|
case Intrinsic::usub_with_overflow:
|
|
case Intrinsic::smul_with_overflow:
|
|
case Intrinsic::umul_with_overflow:
|
|
if (Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue()))
|
|
return TCC_Free;
|
|
else
|
|
return X86TTI::getIntImmCost(Imm, Ty);
|
|
case Intrinsic::experimental_stackmap:
|
|
case Intrinsic::experimental_patchpoint_void:
|
|
case Intrinsic::experimental_patchpoint_i64:
|
|
if (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))
|
|
return TCC_Free;
|
|
else
|
|
return X86TTI::getIntImmCost(Imm, Ty);
|
|
}
|
|
}
|