Andrew Lenharth e4f161c909 Added LSR as a beta pass for alpha ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20407 91177308-0d34-0410-b5e6-96231b3b80d8

2005-03-02 17:21:38 +00:00

..

Alpha

Added LSR as a beta pass for alpha

2005-03-02 17:21:38 +00:00

CBackend

Remove tabs from file.

2005-02-28 19:36:15 +00:00

PowerPC

Add a temporary option for llc-beta: -enable-lsr-for-ppc, which turns on

2005-03-02 06:19:22 +00:00

Skeleton

ignore generated files

2004-11-21 00:01:54 +00:00

Sparc

Substantially improve the code generated by non-folded setcc instructions.

2005-01-01 16:06:57 +00:00

SparcV8

Substantially improve the code generated by non-folded setcc instructions.

2005-01-01 16:06:57 +00:00

SparcV9

Only print out machine instructions before modulo scheduling if we are actually doing modulo scheduling! :)

2005-02-24 02:14:44 +00:00

X86

Fix spelling, patch contributed by Gabor Greif!

2005-02-27 06:18:25 +00:00

Makefile

Build Alpha by default.

2005-01-23 04:34:46 +00:00

MRegisterInfo.cpp

Move destructor out of line to avoid vtable emission in every file that includes the header. Thanks to sabre.

2004-10-27 06:00:53 +00:00

Target.td

Add some bits that can be set for instructions.

2005-01-02 02:27:48 +00:00

TargetData.cpp

Initial support for packed types, contributed by Morten Ofstad

2004-12-01 17:14:28 +00:00

TargetFrameInfo.cpp

Fix compilation errors with VS 2005, patch contributed by Aaron Gray.

2005-02-17 21:40:27 +00:00

TargetInstrInfo.cpp

Finegrainify namespacification

2005-01-19 06:53:34 +00:00

TargetMachine.cpp

Add a new target-independent code generator flag.

2005-01-15 06:00:32 +00:00

TargetMachineRegistry.cpp

…

TargetSchedInfo.cpp

Improve compatiblity with HPUX on Itanium, patch by Duraid Madina

2005-01-16 01:31:31 +00:00