Weiming Zhao e56764bad1 Remove hard coded registers in ARM ldrexd and strexd instructions
This patch replaces the hard coded GPR pair [R0, R1] of
Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with
even/odd GPRPair reg class.
Similar to the lowering of atomic_64 operation.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168207 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16 21:55:34 +00:00
2012-11-14 22:09:20 +00:00
2012-11-16 21:33:35 +00:00
2012-11-14 22:13:56 +00:00
2012-10-09 23:48:34 +00:00
2012-11-14 22:10:47 +00:00
2012-11-14 22:09:20 +00:00
2012-11-16 18:44:36 +00:00
2012-11-14 22:13:56 +00:00
2012-07-11 17:34:12 +00:00

Low Level Virtual Machine (LLVM)
================================

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LLVM backend for 6502
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