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This was done using the Sparc and PowerPC AsmParsers as guides. So far it is very simple and only supports sopp instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221994 91177308-0d34-0410-b5e6-96231b3b80d8
44 lines
1.0 KiB
ReStructuredText
44 lines
1.0 KiB
ReStructuredText
============================
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User Guide for R600 Back-end
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============================
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Introduction
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============
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The R600 back-end provides ISA code generation for AMD GPUs, starting with
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the R600 family up until the current Sea Islands (GCN Gen 2).
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Assembler
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=========
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The assembler is currently a work in progress and not yet complete. Below
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are the currently supported features.
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SOPP Instructions
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-----------------
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Unless otherwise mentioned, all SOPP instructions that with an operand
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accept a integer operand(s) only. No verification is performed on the
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operands, so it is up to the programmer to be familiar with the range
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or acceptable values.
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s_waitcnt
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^^^^^^^^^
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s_waitcnt accepts named arguments to specify which memory counter(s) to
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wait for.
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.. code-block:: nasm
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// Wait for all counters to be 0
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s_waitcnt 0
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// Equivalent to s_waitcnt 0. Counter names can also be delimited by
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// '&' or ','.
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s_waitcnt vmcnt(0) expcnt(0) lgkcmt(0)
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// Wait for vmcnt counter to be 1.
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s_waitcnt vmcnt(1)
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