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https://github.com/c64scene-ar/llvm-6502.git
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e6f32be8df
These will make it easier to test further changes to the code generation and optimization pipelines as those are moved to subtargets initialized with target feature and target cpu. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219106 91177308-0d34-0410-b5e6-96231b3b80d8
79 lines
2.6 KiB
C++
79 lines
2.6 KiB
C++
//==-- AArch64TargetMachine.h - Define TargetMachine for AArch64 -*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the AArch64 specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64TARGETMACHINE_H
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#define LLVM_LIB_TARGET_AARCH64_AARCH64TARGETMACHINE_H
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#include "AArch64InstrInfo.h"
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#include "AArch64Subtarget.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class AArch64TargetMachine : public LLVMTargetMachine {
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protected:
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AArch64Subtarget Subtarget;
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mutable StringMap<std::unique_ptr<AArch64Subtarget>> SubtargetMap;
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public:
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AArch64TargetMachine(const Target &T, StringRef TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL, bool IsLittleEndian);
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const AArch64Subtarget *getSubtargetImpl() const override {
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return &Subtarget;
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}
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const AArch64Subtarget *getSubtargetImpl(const Function &F) const override;
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// Pass Pipeline Configuration
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TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
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/// \brief Register AArch64 analysis passes with a pass manager.
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void addAnalysisPasses(PassManagerBase &PM) override;
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/// \brief Query if the PBQP register allocator is being used
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bool isPBQPUsed() const { return usingPBQP; }
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private:
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bool isLittle;
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bool usingPBQP;
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};
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// AArch64leTargetMachine - AArch64 little endian target machine.
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//
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class AArch64leTargetMachine : public AArch64TargetMachine {
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virtual void anchor();
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public:
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AArch64leTargetMachine(const Target &T, StringRef TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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// AArch64beTargetMachine - AArch64 big endian target machine.
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//
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class AArch64beTargetMachine : public AArch64TargetMachine {
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virtual void anchor();
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public:
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AArch64beTargetMachine(const Target &T, StringRef TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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} // end namespace llvm
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#endif
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