llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-10 02:36:06 +00:00

History

Jakob Stoklund Olesen fd87839a48 Add TRI::getCommonSuperRegClass().

This function is a generalization of getMatchingSuperRegClass() to the
symmetric case where both sides are using a sub-register index. It will
find a super-register class and sub-register indexes that make this
diagram commute:

                                   PreA
                       SuperRC  ---------->  RCA

                          |                   |
                          |                   |
                     PreB |                   | SubA
                          |                   |
                          |                   |
                          V                   V

                         RCB    ----------> SubRC
                                   SubB

This can be used to coalesce copies like:

  %vreg1:sub16 = COPY %vreg2:sub16; GR64:%vreg1, GR32: %vreg2

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156317 91177308-0d34-0410-b5e6-96231b3b80d8

2012-05-07 19:14:58 +00:00

Analysis

Rename the Region::block_iterator to Region::block_node_iterator, and

2012-05-04 20:55:23 +00:00