mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-18 14:31:27 +00:00
e757f00446
because it does not support CMOV of vectors. To implement this efficientlyi, we broadcast the condition bit and use a sequence of NAND-OR to select between the two operands. This is the same sequence we use for targets that don't have vector BLENDs (like SSE2). rdar://12201387 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162926 91177308-0d34-0410-b5e6-96231b3b80d8
18 lines
467 B
LLVM
18 lines
467 B
LLVM
; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s
|
|
; rdar://12201387
|
|
|
|
;CHECK: select_s_v_v
|
|
;CHECK: vbsl
|
|
;CHECK: bx
|
|
define <16 x i8> @select_s_v_v(i32 %avail, i8* %bar) {
|
|
entry:
|
|
%vld1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %bar, i32 1)
|
|
%and = and i32 %avail, 1
|
|
%tobool = icmp eq i32 %and, 0
|
|
%vld1. = select i1 %tobool, <16 x i8> %vld1, <16 x i8> zeroinitializer
|
|
ret <16 x i8> %vld1.
|
|
}
|
|
|
|
declare <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* , i32 )
|
|
|