Evan Cheng e7d6df7353 Add a ARM specific pre-allocation pass that re-schedule loads / stores from ... consecutive addresses togther. This makes it easier for the post-allocation pass to form ldm / stm. This is step 1. We are still missing a lot of ldm / stm opportunities because of register allocation are not done in the desired order. More enhancements coming. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73291 91177308-0d34-0410-b5e6-96231b3b80d8		2009-06-13 09:12:55 +00:00
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Alpha
ARM	Add a ARM specific pre-allocation pass that re-schedule loads / stores from	2009-06-13 09:12:55 +00:00
CBackend	Fix an erroneous check for isFNeg; the FNeg case is handled	2009-06-04 23:43:29 +00:00
CellSPU	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
CPP	Fix code emission for conditional branches.	2009-05-04 19:10:38 +00:00
Generic	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
IA64
Mips	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
MSP430	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
PowerPC	PR3628: Add patterns to match SHL/SRL/SRA to the corresponding Altivec	2009-06-07 01:07:55 +00:00
SPARC	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
X86	Fix Bug 4278: X86-64 with -tailcallopt calling convention	2009-06-12 16:26:57 +00:00
XCore	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00