Jim Grosbach 65c58daa8b Re-enable register scavenging in Thumb1 by default. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83521 91177308-0d34-0410-b5e6-96231b3b80d8

2009-10-08 01:46:59 +00:00

..

SubtargetFeature.h

Switch SubtargetFeature off of ostreams

2009-08-23 21:41:43 +00:00

Target.td

Add instruction flags: hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. When

2009-10-01 08:21:18 +00:00

TargetAsmParser.h

Added the ParseInstruction() hook for target specific assembler directives so

2009-09-10 20:51:44 +00:00

TargetCallingConv.td

Add 'Indirect' LocInfo class and use to pass __m128 on win64. Also minore fixes here and there (mostly __m64).

2009-08-03 08:13:56 +00:00

TargetData.h

Try again at privatizing the layout info map, with a rewritten patch.

2009-08-21 19:59:12 +00:00

TargetELFWriterInfo.h

- Remove custom handling of jumptables by the elf writter (this was

2009-08-05 06:57:03 +00:00

TargetFrameInfo.h

Use explicit structs instead of std::pair to map callee saved regs to spill slots.

2009-09-27 17:58:47 +00:00

TargetInstrDesc.h

Add instruction flags: hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. When

2009-10-01 08:21:18 +00:00

TargetInstrInfo.h

Replace TargetInstrInfo::isInvariantLoad and its target-specific

2009-10-07 17:38:06 +00:00

TargetInstrItineraries.h

Make the end-of-itinerary mark explicit. Some cleanup.

2009-09-24 20:22:50 +00:00

TargetIntrinsicInfo.h

Added support to have TableGen provide information if an intrinsic (core

2009-02-24 23:17:49 +00:00

TargetJITInfo.h

First patch in the direction of splitting MachineCodeEmitter in two subclasses:

2009-05-30 20:51:52 +00:00

TargetLowering.h

Update comments.

2009-09-19 10:08:51 +00:00

TargetLoweringObjectFile.h

Use OutStreamer.SwitchSection instead of writing out textual section directives.

2009-09-30 22:25:37 +00:00

TargetMachine.h

Add a target hook to add pre- post-regalloc scheduling passes.

2009-09-30 08:49:50 +00:00

TargetMachOWriterInfo.h

Don't attribute in file headers anymore. See llvmdev for the

2007-12-29 19:59:42 +00:00

TargetOptions.h

Implement the JIT side of the GDB JIT debugging interface. To enable this

2009-09-20 23:52:43 +00:00

TargetRegisterInfo.h

Re-enable register scavenging in Thumb1 by default.

2009-10-08 01:46:59 +00:00

TargetRegistry.h

remove a dead method.

2009-09-20 22:46:42 +00:00

TargetSchedule.td

Fix apostrophos.

2009-09-15 15:08:33 +00:00

TargetSelect.h

Add llvm::InitializeAllTargetInfos and llvm::InitializeAllAsmParsers.

2009-07-17 22:35:35 +00:00

TargetSelectionDAG.td

Add a new "SDTCisVec" SDTypeConstraint. This complements the vAny type.

2009-08-12 22:30:59 +00:00

TargetSubtarget.h

Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.

2009-09-30 00:10:16 +00:00