mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-10 02:36:06 +00:00
35b3df6e31
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168886 91177308-0d34-0410-b5e6-96231b3b80d8
190 lines
5.3 KiB
LLVM
190 lines
5.3 KiB
LLVM
; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s
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define i64 @test1(i64* %ptr, i64 %val) {
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; CHECK: test1:
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; CHECK: dmb ish
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: adds [[REG3:(r[0-9]?[02468])]], [[REG1]]
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; CHECK: adc [[REG4:(r[0-9]?[13579])]], [[REG2]]
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; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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%r = atomicrmw add i64* %ptr, i64 %val seq_cst
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ret i64 %r
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}
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define i64 @test2(i64* %ptr, i64 %val) {
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; CHECK: test2:
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; CHECK: dmb ish
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: subs [[REG3:(r[0-9]?[02468])]], [[REG1]]
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; CHECK: sbc [[REG4:(r[0-9]?[13579])]], [[REG2]]
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; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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%r = atomicrmw sub i64* %ptr, i64 %val seq_cst
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ret i64 %r
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}
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define i64 @test3(i64* %ptr, i64 %val) {
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; CHECK: test3:
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; CHECK: dmb ish
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: and [[REG3:(r[0-9]?[02468])]], [[REG1]]
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; CHECK: and [[REG4:(r[0-9]?[13579])]], [[REG2]]
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; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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%r = atomicrmw and i64* %ptr, i64 %val seq_cst
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ret i64 %r
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}
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define i64 @test4(i64* %ptr, i64 %val) {
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; CHECK: test4:
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; CHECK: dmb ish
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: orr [[REG3:(r[0-9]?[02468])]], [[REG1]]
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; CHECK: orr [[REG4:(r[0-9]?[13579])]], [[REG2]]
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; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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%r = atomicrmw or i64* %ptr, i64 %val seq_cst
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ret i64 %r
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}
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define i64 @test5(i64* %ptr, i64 %val) {
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; CHECK: test5:
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; CHECK: dmb ish
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: eor [[REG3:(r[0-9]?[02468])]], [[REG1]]
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; CHECK: eor [[REG4:(r[0-9]?[13579])]], [[REG2]]
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; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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%r = atomicrmw xor i64* %ptr, i64 %val seq_cst
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ret i64 %r
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}
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define i64 @test6(i64* %ptr, i64 %val) {
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; CHECK: test6:
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; CHECK: dmb ish
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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%r = atomicrmw xchg i64* %ptr, i64 %val seq_cst
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ret i64 %r
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}
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define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) {
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; CHECK: test7:
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; CHECK: dmb ish
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: cmp [[REG1]]
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; CHECK: cmpeq [[REG2]]
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; CHECK: bne
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; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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%r = cmpxchg i64* %ptr, i64 %val1, i64 %val2 seq_cst
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ret i64 %r
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}
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; Compiles down to cmpxchg
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; FIXME: Should compile to a single ldrexd
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define i64 @test8(i64* %ptr) {
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; CHECK: test8:
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: cmp [[REG1]]
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; CHECK: cmpeq [[REG2]]
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; CHECK: bne
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; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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%r = load atomic i64* %ptr seq_cst, align 8
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ret i64 %r
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}
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; Compiles down to atomicrmw xchg; there really isn't any more efficient
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; way to write it.
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define void @test9(i64* %ptr, i64 %val) {
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; CHECK: test9:
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; CHECK: dmb ish
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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store atomic i64 %val, i64* %ptr seq_cst, align 8
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ret void
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}
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define i64 @test10(i64* %ptr, i64 %val) {
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; CHECK: test10:
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; CHECK: dmb ish
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
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; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
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; CHECK: ble
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; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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%r = atomicrmw min i64* %ptr, i64 %val seq_cst
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ret i64 %r
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}
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define i64 @test11(i64* %ptr, i64 %val) {
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; CHECK: test11:
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; CHECK: dmb ish
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
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; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
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; CHECK: bls
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; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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%r = atomicrmw umin i64* %ptr, i64 %val seq_cst
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ret i64 %r
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}
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define i64 @test12(i64* %ptr, i64 %val) {
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; CHECK: test12:
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; CHECK: dmb ish
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
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; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
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; CHECK: bge
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; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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%r = atomicrmw max i64* %ptr, i64 %val seq_cst
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ret i64 %r
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}
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define i64 @test13(i64* %ptr, i64 %val) {
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; CHECK: test13:
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; CHECK: dmb ish
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
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; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
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; CHECK: bhs
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; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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%r = atomicrmw umax i64* %ptr, i64 %val seq_cst
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ret i64 %r
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}
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