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	Summary: No functional change since these predicates are (currently) synonymous. Extracted from a patch by David Chisnall His work was sponsored by: DARPA, AFRL Differential Revision: http://llvm-reviews.chandlerc.com/D3202 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204943 91177308-0d34-0410-b5e6-96231b3b80d8
		
			
				
	
	
		
			203 lines
		
	
	
		
			6.9 KiB
		
	
	
	
		
			C++
		
	
	
	
	
	
			
		
		
	
	
			203 lines
		
	
	
		
			6.9 KiB
		
	
	
	
		
			C++
		
	
	
	
	
	
//===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the Mips specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-subtarget"
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#include "MipsMachineFunction.h"
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#include "Mips.h"
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#include "MipsRegisterInfo.h"
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#include "MipsSubtarget.h"
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#include "MipsTargetMachine.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "MipsGenSubtargetInfo.inc"
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using namespace llvm;
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// FIXME: Maybe this should be on by default when Mips16 is specified
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//
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static cl::opt<bool> Mixed16_32(
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  "mips-mixed-16-32",
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  cl::init(false),
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  cl::desc("Allow for a mixture of Mips16 "
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           "and Mips32 code in a single source file"),
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  cl::Hidden);
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static cl::opt<bool> Mips_Os16(
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  "mips-os16",
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  cl::init(false),
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  cl::desc("Compile all functions that don' use "
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           "floating point as Mips 16"),
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  cl::Hidden);
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static cl::opt<bool>
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Mips16HardFloat("mips16-hard-float", cl::NotHidden,
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                cl::desc("MIPS: mips16 hard float enable."),
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                cl::init(false));
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static cl::opt<bool>
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Mips16ConstantIslands(
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  "mips16-constant-islands", cl::NotHidden,
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  cl::desc("MIPS: mips16 constant islands enable."),
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  cl::init(true));
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/// Select the Mips CPU for the given triple and cpu name.
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/// FIXME: Merge with the copy in MipsMCTargetDesc.cpp
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static inline StringRef selectMipsCPU(StringRef TT, StringRef CPU) {
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  if (CPU.empty() || CPU == "generic") {
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    Triple TheTriple(TT);
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    if (TheTriple.getArch() == Triple::mips ||
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        TheTriple.getArch() == Triple::mipsel)
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      CPU = "mips32";
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    else
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      CPU = "mips64";
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  }
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  return CPU;
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}
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void MipsSubtarget::anchor() { }
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MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
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                             const std::string &FS, bool little,
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                             Reloc::Model _RM, MipsTargetMachine *_TM) :
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  MipsGenSubtargetInfo(TT, CPU, FS),
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  MipsArchVersion(Mips32), MipsABI(UnknownABI), IsLittle(little),
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  IsSingleFloat(false), IsFP64bit(false), IsGP64bit(false), HasVFPU(false),
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  HasCnMips(false), IsLinux(true), HasSEInReg(false), HasCondMov(false),
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  HasSwap(false), HasBitCount(false), HasFPIdx(false),
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  InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
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  InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
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  AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
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  RM(_RM), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT)
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{
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  std::string CPUName = CPU;
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  CPUName = selectMipsCPU(TT, CPUName);
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  // Parse features string.
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  ParseSubtargetFeatures(CPUName, FS);
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  if (InMips16Mode && !TM->Options.UseSoftFloat) {
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    // Hard float for mips16 means essentially to compile as soft float
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    // but to use a runtime library for soft float that is written with
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    // native mips32 floating point instructions (those runtime routines
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    // run in mips32 hard float mode).
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    TM->Options.UseSoftFloat = true;
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    TM->Options.FloatABIType = FloatABI::Soft;
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    InMips16HardFloat = true;
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  }
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  PreviousInMips16Mode = InMips16Mode;
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  // Initialize scheduling itinerary for the specified CPU.
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  InstrItins = getInstrItineraryForCPU(CPUName);
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  // Assert exactly one ABI was chosen.
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  assert(MipsABI != UnknownABI);
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  assert((((getFeatureBits() & Mips::FeatureO32) != 0) +
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          ((getFeatureBits() & Mips::FeatureEABI) != 0) +
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          ((getFeatureBits() & Mips::FeatureN32) != 0) +
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          ((getFeatureBits() & Mips::FeatureN64) != 0)) == 1);
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  // Check if Architecture and ABI are compatible.
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  assert(((!isGP64bit() && (isABI_O32() || isABI_EABI())) ||
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          (isGP64bit() && (isABI_N32() || isABI_N64()))) &&
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         "Invalid  Arch & ABI pair.");
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  if (hasMSA() && !isFP64bit())
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    report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
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                       "See -mattr=+fp64.",
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                       false);
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  // Is the target system Linux ?
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  if (TT.find("linux") == std::string::npos)
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    IsLinux = false;
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  // Set UseSmallSection.
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  UseSmallSection = !IsLinux && (RM == Reloc::Static);
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  // set some subtarget specific features
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  if (inMips16Mode())
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    HasBitCount=false;
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}
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bool
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MipsSubtarget::enablePostRAScheduler(CodeGenOpt::Level OptLevel,
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                                    TargetSubtargetInfo::AntiDepBreakMode &Mode,
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                                     RegClassVector &CriticalPathRCs) const {
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  Mode = TargetSubtargetInfo::ANTIDEP_NONE;
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  CriticalPathRCs.clear();
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  CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass
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                                        : &Mips::GPR32RegClass);
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  return OptLevel >= CodeGenOpt::Aggressive;
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}
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//FIXME: This logic for reseting the subtarget along with
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// the helper classes can probably be simplified but there are a lot of
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// cases so we will defer rewriting this to later.
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//
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void MipsSubtarget::resetSubtarget(MachineFunction *MF) {
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  bool ChangeToMips16 = false, ChangeToNoMips16 = false;
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  DEBUG(dbgs() << "resetSubtargetFeatures" << "\n");
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  AttributeSet FnAttrs = MF->getFunction()->getAttributes();
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  ChangeToMips16 = FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
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                                        "mips16");
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  ChangeToNoMips16 = FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
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                                        "nomips16");
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  assert (!(ChangeToMips16 & ChangeToNoMips16) &&
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          "mips16 and nomips16 specified on the same function");
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  if (ChangeToMips16) {
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    if (PreviousInMips16Mode)
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      return;
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    OverrideMode = Mips16Override;
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    PreviousInMips16Mode = true;
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    TM->setHelperClassesMips16();
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    return;
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  } else if (ChangeToNoMips16) {
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    if (!PreviousInMips16Mode)
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      return;
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    OverrideMode = NoMips16Override;
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    PreviousInMips16Mode = false;
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    TM->setHelperClassesMipsSE();
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    return;
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  } else {
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    if (OverrideMode == NoOverride)
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      return;
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    OverrideMode = NoOverride;
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    DEBUG(dbgs() << "back to default" << "\n");
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    if (inMips16Mode() && !PreviousInMips16Mode) {
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      TM->setHelperClassesMips16();
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      PreviousInMips16Mode = true;
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    } else if (!inMips16Mode() && PreviousInMips16Mode) {
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      TM->setHelperClassesMipsSE();
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      PreviousInMips16Mode = false;
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    }
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    return;
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  }
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}
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bool MipsSubtarget::mipsSEUsesSoftFloat() const {
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  return TM->Options.UseSoftFloat && !InMips16HardFloat;
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}
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bool MipsSubtarget::useConstantIslands() {
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  DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n");
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  return Mips16ConstantIslands;
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}
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