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38a80e9b21
I'm under the impression that we used to infer the isCommutable flag from the instruction-associated pattern. Regardless, we don't seem to do this (at least by default) any more. I've gone through all of our instruction definitions, and marked as commutative all of those that should be trivial to commute (by exchanging the first two operands). There has been special code for the RL* instructions, and that's not changed. Before this change, we had the following commutative instructions: RLDIMI RLDIMIo RLWIMI RLWIMI8 RLWIMI8o RLWIMIo XSADDDP XSMULDP XVADDDP XVADDSP XVMULDP XVMULSP After: ADD4 ADD4o ADD8 ADD8o ADDC ADDC8 ADDC8o ADDCo ADDE ADDE8 ADDE8o ADDEo AND AND8 AND8o ANDo CRAND CREQV CRNAND CRNOR CROR CRXOR EQV EQV8 EQV8o EQVo FADD FADDS FADDSo FADDo FMADD FMADDS FMADDSo FMADDo FMSUB FMSUBS FMSUBSo FMSUBo FMUL FMULS FMULSo FMULo FNMADD FNMADDS FNMADDSo FNMADDo FNMSUB FNMSUBS FNMSUBSo FNMSUBo MULHD MULHDU MULHDUo MULHDo MULHW MULHWU MULHWUo MULHWo MULLD MULLDo MULLW MULLWo NAND NAND8 NAND8o NANDo NOR NOR8 NOR8o NORo OR OR8 OR8o ORo RLDIMI RLDIMIo RLWIMI RLWIMI8 RLWIMI8o RLWIMIo VADDCUW VADDFP VADDSBS VADDSHS VADDSWS VADDUBM VADDUBS VADDUHM VADDUHS VADDUWM VADDUWS VAND VAVGSB VAVGSH VAVGSW VAVGUB VAVGUH VAVGUW VMADDFP VMAXFP VMAXSB VMAXSH VMAXSW VMAXUB VMAXUH VMAXUW VMHADDSHS VMHRADDSHS VMINFP VMINSB VMINSH VMINSW VMINUB VMINUH VMINUW VMLADDUHM VMULESB VMULESH VMULEUB VMULEUH VMULOSB VMULOSH VMULOUB VMULOUH VNMSUBFP VOR VXOR XOR XOR8 XOR8o XORo XSADDDP XSMADDADP XSMAXDP XSMINDP XSMSUBADP XSMULDP XSNMADDADP XSNMSUBADP XVADDDP XVADDSP XVMADDADP XVMADDASP XVMAXDP XVMAXSP XVMINDP XVMINSP XVMSUBADP XVMSUBASP XVMULDP XVMULSP XVNMADDADP XVNMADDASP XVNMSUBADP XVNMSUBASP XXLAND XXLNOR XXLOR XXLXOR This is a by-inspection change, and I'm not sure how to write a reliable test case. I would like advice on this, however. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204609 91177308-0d34-0410-b5e6-96231b3b80d8
703 lines
33 KiB
TableGen
703 lines
33 KiB
TableGen
//===- PPCInstrVSX.td - The PowerPC VSX Extension --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the VSX extension to the PowerPC instruction set.
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//
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//===----------------------------------------------------------------------===//
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def PPCRegVSRCAsmOperand : AsmOperandClass {
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let Name = "RegVSRC"; let PredicateMethod = "isVSRegNumber";
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}
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def vsrc : RegisterOperand<VSRC> {
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let ParserMatchClass = PPCRegVSRCAsmOperand;
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}
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multiclass XX3Form_Rcr<bits<6> opcode, bits<7> xo, dag OOL, dag IOL,
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string asmbase, string asmstr, InstrItinClass itin,
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list<dag> pattern> {
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let BaseName = asmbase in {
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def NAME : XX3Form_Rc<opcode, xo, OOL, IOL,
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!strconcat(asmbase, !strconcat(" ", asmstr)), itin,
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pattern>;
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let Defs = [CR6] in
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def o : XX3Form_Rc<opcode, xo, OOL, IOL,
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!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
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[]>, isDOT;
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}
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}
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def HasVSX : Predicate<"PPCSubTarget.hasVSX()">;
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let Predicates = [HasVSX] in {
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let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
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let neverHasSideEffects = 1 in { // VSX instructions don't have side effects.
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let Uses = [RM] in {
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// Load indexed instructions
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let mayLoad = 1, canFoldAsLoad = 1 in {
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def LXSDX : XForm_1<31, 588,
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(outs vsrc:$XT), (ins memrr:$src),
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"lxsdx $XT, $src", IIC_LdStLFD,
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[(set f64:$XT, (load xoaddr:$src))]>;
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def LXVD2X : XForm_1<31, 844,
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(outs vsrc:$XT), (ins memrr:$src),
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"lxvd2x $XT, $src", IIC_LdStLFD,
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[(set v2f64:$XT, (load xoaddr:$src))]>;
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def LXVDSX : XForm_1<31, 332,
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(outs vsrc:$XT), (ins memrr:$src),
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"lxvdsx $XT, $src", IIC_LdStLFD, []>;
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// TODO: match load + splat to lxvdsx.
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def LXVW4X : XForm_1<31, 780,
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(outs vsrc:$XT), (ins memrr:$src),
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"lxvw4x $XT, $src", IIC_LdStLFD,
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[(set v4f32:$XT, (load xoaddr:$src))]>;
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}
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// Store indexed instructions
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let mayStore = 1 in {
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def STXSDX : XX1Form<31, 716,
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(outs), (ins vsrc:$XT, memrr:$dst),
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"stxsdx $XT, $dst", IIC_LdStSTFD,
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[(store f64:$XT, xoaddr:$dst)]>;
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def STXVD2X : XX1Form<31, 972,
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(outs), (ins vsrc:$XT, memrr:$dst),
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"stxvd2x $XT, $dst", IIC_LdStSTFD,
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[(store v2f64:$XT, xoaddr:$dst)]>;
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def STXVW4X : XX1Form<31, 908,
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(outs), (ins vsrc:$XT, memrr:$dst),
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"stxvw4x $XT, $dst", IIC_LdStSTFD,
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[(store v4f32:$XT, xoaddr:$dst)]>;
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}
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// Add/Mul Instructions
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let isCommutable = 1 in {
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def XSADDDP : XX3Form<60, 32,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xsadddp $XT, $XA, $XB", IIC_VecFP,
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[(set f64:$XT, (fadd f64:$XA, f64:$XB))]>;
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def XSMULDP : XX3Form<60, 48,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xsmuldp $XT, $XA, $XB", IIC_VecFP,
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[(set f64:$XT, (fmul f64:$XA, f64:$XB))]>;
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def XVADDDP : XX3Form<60, 96,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvadddp $XT, $XA, $XB", IIC_VecFP,
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[(set v2f64:$XT, (fadd v2f64:$XA, v2f64:$XB))]>;
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def XVADDSP : XX3Form<60, 64,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvaddsp $XT, $XA, $XB", IIC_VecFP,
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[(set v4f32:$XT, (fadd v4f32:$XA, v4f32:$XB))]>;
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def XVMULDP : XX3Form<60, 112,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvmuldp $XT, $XA, $XB", IIC_VecFP,
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[(set v2f64:$XT, (fmul v2f64:$XA, v2f64:$XB))]>;
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def XVMULSP : XX3Form<60, 80,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvmulsp $XT, $XA, $XB", IIC_VecFP,
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[(set v4f32:$XT, (fmul v4f32:$XA, v4f32:$XB))]>;
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}
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// Subtract Instructions
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def XSSUBDP : XX3Form<60, 40,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xssubdp $XT, $XA, $XB", IIC_VecFP,
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[(set f64:$XT, (fsub f64:$XA, f64:$XB))]>;
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def XVSUBDP : XX3Form<60, 104,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvsubdp $XT, $XA, $XB", IIC_VecFP,
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[(set v2f64:$XT, (fsub v2f64:$XA, v2f64:$XB))]>;
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def XVSUBSP : XX3Form<60, 72,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvsubsp $XT, $XA, $XB", IIC_VecFP,
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[(set v4f32:$XT, (fsub v4f32:$XA, v4f32:$XB))]>;
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// FMA Instructions
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let isCommutable = 1 in
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def XSMADDADP : XX3Form<60, 33,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xsmaddadp $XT, $XA, $XB", IIC_VecFP,
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[(set f64:$XT, (fma f64:$XA, f64:$XB, f64:$XTi))]>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
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def XSMADDMDP : XX3Form<60, 41,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xsmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
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// TODO: Select between these based first on whether one of the operands has
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// no further uses. We probably want to do this after scheduling but before
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// register allocation.
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let isCommutable = 1 in
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def XSMSUBADP : XX3Form<60, 49,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xsmsubadp $XT, $XA, $XB", IIC_VecFP,
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[(set f64:$XT, (fma f64:$XA, f64:$XB, (fneg f64:$XTi)))]>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
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def XSMSUBMDP : XX3Form<60, 57,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xsmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
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let isCommutable = 1 in
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def XSNMADDADP : XX3Form<60, 161,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xsnmaddadp $XT, $XA, $XB", IIC_VecFP,
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[(set f64:$XT, (fneg (fma f64:$XA, f64:$XB, f64:$XTi)))]>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
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def XSNMADDMDP : XX3Form<60, 169,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xsnmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
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let isCommutable = 1 in
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def XSNMSUBADP : XX3Form<60, 177,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xsnmsubadp $XT, $XA, $XB", IIC_VecFP,
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[(set f64:$XT, (fneg (fma f64:$XA, f64:$XB, (fneg f64:$XTi))))]>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
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def XSNMSUBMDP : XX3Form<60, 185,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xsnmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
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let isCommutable = 1 in
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def XVMADDADP : XX3Form<60, 97,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvmaddadp $XT, $XA, $XB", IIC_VecFP,
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[(set v2f64:$XT, (fma v2f64:$XA, v2f64:$XB, v2f64:$XTi))]>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
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def XVMADDMDP : XX3Form<60, 105,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
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let isCommutable = 1 in
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def XVMADDASP : XX3Form<60, 65,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvmaddasp $XT, $XA, $XB", IIC_VecFP,
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[(set v4f32:$XT, (fma v4f32:$XA, v4f32:$XB, v4f32:$XTi))]>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
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def XVMADDMSP : XX3Form<60, 73,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
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let isCommutable = 1 in
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def XVMSUBADP : XX3Form<60, 113,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvmsubadp $XT, $XA, $XB", IIC_VecFP,
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[(set v2f64:$XT, (fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi)))]>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
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def XVMSUBMDP : XX3Form<60, 121,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
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let isCommutable = 1 in
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def XVMSUBASP : XX3Form<60, 81,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvmsubasp $XT, $XA, $XB", IIC_VecFP,
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[(set v4f32:$XT, (fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi)))]>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
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def XVMSUBMSP : XX3Form<60, 89,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
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let isCommutable = 1 in
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def XVNMADDADP : XX3Form<60, 225,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvnmaddadp $XT, $XA, $XB", IIC_VecFP,
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[(set v2f64:$XT, (fneg (fma v2f64:$XA, v2f64:$XB, v2f64:$XTi)))]>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
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def XVNMADDMDP : XX3Form<60, 233,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvnmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
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let isCommutable = 1 in
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def XVNMADDASP : XX3Form<60, 193,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvnmaddasp $XT, $XA, $XB", IIC_VecFP,
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[(set v4f32:$XT, (fneg (fma v4f32:$XA, v4f32:$XB, v4f32:$XTi)))]>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
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def XVNMADDMSP : XX3Form<60, 201,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvnmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
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let isCommutable = 1 in
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def XVNMSUBADP : XX3Form<60, 241,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvnmsubadp $XT, $XA, $XB", IIC_VecFP,
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[(set v2f64:$XT, (fneg (fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi))))]>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
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def XVNMSUBMDP : XX3Form<60, 249,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvnmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
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let isCommutable = 1 in
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def XVNMSUBASP : XX3Form<60, 209,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvnmsubasp $XT, $XA, $XB", IIC_VecFP,
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[(set v4f32:$XT, (fneg (fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi))))]>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
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def XVNMSUBMSP : XX3Form<60, 217,
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(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
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"xvnmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
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// Division Instructions
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def XSDIVDP : XX3Form<60, 56,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xsdivdp $XT, $XA, $XB", IIC_VecFP,
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[(set f64:$XT, (fdiv f64:$XA, f64:$XB))]>;
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def XSSQRTDP : XX2Form<60, 75,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xssqrtdp $XT, $XB", IIC_VecFP,
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[(set f64:$XT, (fsqrt f64:$XB))]>;
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def XSREDP : XX2Form<60, 90,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xsredp $XT, $XB", IIC_VecFP,
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[(set f64:$XT, (PPCfre f64:$XB))]>;
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def XSRSQRTEDP : XX2Form<60, 74,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xsrsqrtedp $XT, $XB", IIC_VecFP,
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[(set f64:$XT, (PPCfrsqrte f64:$XB))]>;
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def XSTDIVDP : XX3Form_1<60, 61,
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(outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB),
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"xstdivdp $crD, $XA, $XB", IIC_VecFP, []>;
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def XSTSQRTDP : XX2Form_1<60, 106,
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(outs crrc:$crD), (ins vsrc:$XB),
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"xstsqrtdp $crD, $XB", IIC_VecFP, []>;
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def XVDIVDP : XX3Form<60, 120,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvdivdp $XT, $XA, $XB", IIC_VecFP,
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[(set v2f64:$XT, (fdiv v2f64:$XA, v2f64:$XB))]>;
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def XVDIVSP : XX3Form<60, 88,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvdivsp $XT, $XA, $XB", IIC_VecFP,
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[(set v4f32:$XT, (fdiv v4f32:$XA, v4f32:$XB))]>;
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def XVSQRTDP : XX2Form<60, 203,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvsqrtdp $XT, $XB", IIC_VecFP,
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[(set v2f64:$XT, (fsqrt v2f64:$XB))]>;
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def XVSQRTSP : XX2Form<60, 139,
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(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvsqrtsp $XT, $XB", IIC_VecFP,
|
|
[(set v4f32:$XT, (fsqrt v4f32:$XB))]>;
|
|
|
|
def XVTDIVDP : XX3Form_1<60, 125,
|
|
(outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB),
|
|
"xvtdivdp $crD, $XA, $XB", IIC_VecFP, []>;
|
|
def XVTDIVSP : XX3Form_1<60, 93,
|
|
(outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB),
|
|
"xvtdivsp $crD, $XA, $XB", IIC_VecFP, []>;
|
|
|
|
def XVTSQRTDP : XX2Form_1<60, 234,
|
|
(outs crrc:$crD), (ins vsrc:$XB),
|
|
"xvtsqrtdp $crD, $XB", IIC_VecFP, []>;
|
|
def XVTSQRTSP : XX2Form_1<60, 170,
|
|
(outs crrc:$crD), (ins vsrc:$XB),
|
|
"xvtsqrtsp $crD, $XB", IIC_VecFP, []>;
|
|
|
|
def XVREDP : XX2Form<60, 218,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvredp $XT, $XB", IIC_VecFP,
|
|
[(set v2f64:$XT, (PPCfre v2f64:$XB))]>;
|
|
def XVRESP : XX2Form<60, 154,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvresp $XT, $XB", IIC_VecFP,
|
|
[(set v4f32:$XT, (PPCfre v4f32:$XB))]>;
|
|
|
|
def XVRSQRTEDP : XX2Form<60, 202,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvrsqrtedp $XT, $XB", IIC_VecFP,
|
|
[(set v2f64:$XT, (PPCfrsqrte v2f64:$XB))]>;
|
|
def XVRSQRTESP : XX2Form<60, 138,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvrsqrtesp $XT, $XB", IIC_VecFP,
|
|
[(set v4f32:$XT, (PPCfrsqrte v4f32:$XB))]>;
|
|
|
|
// Compare Instructions
|
|
def XSCMPODP : XX3Form_1<60, 43,
|
|
(outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB),
|
|
"xscmpodp $crD, $XA, $XB", IIC_VecFPCompare, []>;
|
|
def XSCMPUDP : XX3Form_1<60, 35,
|
|
(outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB),
|
|
"xscmpudp $crD, $XA, $XB", IIC_VecFPCompare, []>;
|
|
|
|
defm XVCMPEQDP : XX3Form_Rcr<60, 99,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xvcmpeqdp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
|
|
defm XVCMPEQSP : XX3Form_Rcr<60, 67,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xvcmpeqsp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
|
|
defm XVCMPGEDP : XX3Form_Rcr<60, 115,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xvcmpgedp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
|
|
defm XVCMPGESP : XX3Form_Rcr<60, 83,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xvcmpgesp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
|
|
defm XVCMPGTDP : XX3Form_Rcr<60, 107,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xvcmpgtdp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
|
|
defm XVCMPGTSP : XX3Form_Rcr<60, 75,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xvcmpgtsp", "$XT, $XA, $XB", IIC_VecFPCompare, []>;
|
|
|
|
// Move Instructions
|
|
def XSABSDP : XX2Form<60, 345,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xsabsdp $XT, $XB", IIC_VecFP,
|
|
[(set f64:$XT, (fabs f64:$XB))]>;
|
|
def XSNABSDP : XX2Form<60, 361,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xsnabsdp $XT, $XB", IIC_VecFP,
|
|
[(set f64:$XT, (fneg (fabs f64:$XB)))]>;
|
|
def XSNEGDP : XX2Form<60, 377,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xsnegdp $XT, $XB", IIC_VecFP,
|
|
[(set f64:$XT, (fneg f64:$XB))]>;
|
|
def XSCPSGNDP : XX3Form<60, 176,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xscpsgndp $XT, $XA, $XB", IIC_VecFP,
|
|
[(set f64:$XT, (fcopysign f64:$XB, f64:$XA))]>;
|
|
|
|
def XVABSDP : XX2Form<60, 473,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvabsdp $XT, $XB", IIC_VecFP,
|
|
[(set v2f64:$XT, (fabs v2f64:$XB))]>;
|
|
|
|
def XVABSSP : XX2Form<60, 409,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvabssp $XT, $XB", IIC_VecFP,
|
|
[(set v4f32:$XT, (fabs v4f32:$XB))]>;
|
|
|
|
def XVCPSGNDP : XX3Form<60, 240,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xvcpsgndp $XT, $XA, $XB", IIC_VecFP,
|
|
[(set v2f64:$XT, (fcopysign v2f64:$XB, v2f64:$XA))]>;
|
|
def XVCPSGNSP : XX3Form<60, 208,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xvcpsgnsp $XT, $XA, $XB", IIC_VecFP,
|
|
[(set v4f32:$XT, (fcopysign v4f32:$XB, v4f32:$XA))]>;
|
|
|
|
def XVNABSDP : XX2Form<60, 489,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvnabsdp $XT, $XB", IIC_VecFP,
|
|
[(set v2f64:$XT, (fneg (fabs v2f64:$XB)))]>;
|
|
def XVNABSSP : XX2Form<60, 425,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvnabssp $XT, $XB", IIC_VecFP,
|
|
[(set v4f32:$XT, (fneg (fabs v4f32:$XB)))]>;
|
|
|
|
def XVNEGDP : XX2Form<60, 505,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvnegdp $XT, $XB", IIC_VecFP,
|
|
[(set v2f64:$XT, (fneg v2f64:$XB))]>;
|
|
def XVNEGSP : XX2Form<60, 441,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvnegsp $XT, $XB", IIC_VecFP,
|
|
[(set v4f32:$XT, (fneg v4f32:$XB))]>;
|
|
|
|
// Conversion Instructions
|
|
def XSCVDPSP : XX2Form<60, 265,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xscvdpsp $XT, $XB", IIC_VecFP, []>;
|
|
def XSCVDPSXDS : XX2Form<60, 344,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xscvdpsxds $XT, $XB", IIC_VecFP,
|
|
[(set f64:$XT, (PPCfctidz f64:$XB))]>;
|
|
def XSCVDPSXWS : XX2Form<60, 88,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xscvdpsxws $XT, $XB", IIC_VecFP,
|
|
[(set f64:$XT, (PPCfctiwz f64:$XB))]>;
|
|
def XSCVDPUXDS : XX2Form<60, 328,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xscvdpuxds $XT, $XB", IIC_VecFP,
|
|
[(set f64:$XT, (PPCfctiduz f64:$XB))]>;
|
|
def XSCVDPUXWS : XX2Form<60, 72,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xscvdpuxws $XT, $XB", IIC_VecFP,
|
|
[(set f64:$XT, (PPCfctiwuz f64:$XB))]>;
|
|
def XSCVSPDP : XX2Form<60, 329,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xscvspdp $XT, $XB", IIC_VecFP, []>;
|
|
def XSCVSXDDP : XX2Form<60, 376,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xscvsxddp $XT, $XB", IIC_VecFP,
|
|
[(set f64:$XT, (PPCfcfid f64:$XB))]>;
|
|
def XSCVUXDDP : XX2Form<60, 360,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xscvuxddp $XT, $XB", IIC_VecFP,
|
|
[(set f64:$XT, (PPCfcfidu f64:$XB))]>;
|
|
|
|
def XVCVDPSP : XX2Form<60, 393,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvcvdpsp $XT, $XB", IIC_VecFP, []>;
|
|
def XVCVDPSXDS : XX2Form<60, 472,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvcvdpsxds $XT, $XB", IIC_VecFP, []>;
|
|
def XVCVDPSXWS : XX2Form<60, 216,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvcvdpsxws $XT, $XB", IIC_VecFP, []>;
|
|
def XVCVDPUXDS : XX2Form<60, 456,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvcvdpuxds $XT, $XB", IIC_VecFP, []>;
|
|
def XVCVDPUXWS : XX2Form<60, 200,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvcvdpuxws $XT, $XB", IIC_VecFP, []>;
|
|
|
|
def XVCVSPDP : XX2Form<60, 457,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvcvspdp $XT, $XB", IIC_VecFP, []>;
|
|
def XVCVSPSXDS : XX2Form<60, 408,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvcvspsxds $XT, $XB", IIC_VecFP, []>;
|
|
def XVCVSPSXWS : XX2Form<60, 152,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvcvspsxws $XT, $XB", IIC_VecFP, []>;
|
|
def XVCVSPUXDS : XX2Form<60, 392,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvcvspuxds $XT, $XB", IIC_VecFP, []>;
|
|
def XVCVSPUXWS : XX2Form<60, 136,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvcvspuxws $XT, $XB", IIC_VecFP, []>;
|
|
def XVCVSXDDP : XX2Form<60, 504,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvcvsxddp $XT, $XB", IIC_VecFP, []>;
|
|
def XVCVSXDSP : XX2Form<60, 440,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvcvsxdsp $XT, $XB", IIC_VecFP, []>;
|
|
def XVCVSXWDP : XX2Form<60, 248,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvcvsxwdp $XT, $XB", IIC_VecFP, []>;
|
|
def XVCVSXWSP : XX2Form<60, 184,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvcvsxwsp $XT, $XB", IIC_VecFP, []>;
|
|
def XVCVUXDDP : XX2Form<60, 488,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvcvuxddp $XT, $XB", IIC_VecFP, []>;
|
|
def XVCVUXDSP : XX2Form<60, 424,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvcvuxdsp $XT, $XB", IIC_VecFP, []>;
|
|
def XVCVUXWDP : XX2Form<60, 232,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvcvuxwdp $XT, $XB", IIC_VecFP, []>;
|
|
def XVCVUXWSP : XX2Form<60, 168,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvcvuxwsp $XT, $XB", IIC_VecFP, []>;
|
|
|
|
// Rounding Instructions
|
|
def XSRDPI : XX2Form<60, 73,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xsrdpi $XT, $XB", IIC_VecFP,
|
|
[(set f64:$XT, (frnd f64:$XB))]>;
|
|
def XSRDPIC : XX2Form<60, 107,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xsrdpic $XT, $XB", IIC_VecFP,
|
|
[(set f64:$XT, (fnearbyint f64:$XB))]>;
|
|
def XSRDPIM : XX2Form<60, 121,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xsrdpim $XT, $XB", IIC_VecFP,
|
|
[(set f64:$XT, (ffloor f64:$XB))]>;
|
|
def XSRDPIP : XX2Form<60, 105,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xsrdpip $XT, $XB", IIC_VecFP,
|
|
[(set f64:$XT, (fceil f64:$XB))]>;
|
|
def XSRDPIZ : XX2Form<60, 89,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xsrdpiz $XT, $XB", IIC_VecFP,
|
|
[(set f64:$XT, (ftrunc f64:$XB))]>;
|
|
|
|
def XVRDPI : XX2Form<60, 201,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvrdpi $XT, $XB", IIC_VecFP,
|
|
[(set v2f64:$XT, (frnd v2f64:$XB))]>;
|
|
def XVRDPIC : XX2Form<60, 235,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvrdpic $XT, $XB", IIC_VecFP,
|
|
[(set v2f64:$XT, (fnearbyint v2f64:$XB))]>;
|
|
def XVRDPIM : XX2Form<60, 249,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvrdpim $XT, $XB", IIC_VecFP,
|
|
[(set v2f64:$XT, (ffloor v2f64:$XB))]>;
|
|
def XVRDPIP : XX2Form<60, 233,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvrdpip $XT, $XB", IIC_VecFP,
|
|
[(set v2f64:$XT, (fceil v2f64:$XB))]>;
|
|
def XVRDPIZ : XX2Form<60, 217,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvrdpiz $XT, $XB", IIC_VecFP,
|
|
[(set v2f64:$XT, (ftrunc v2f64:$XB))]>;
|
|
|
|
def XVRSPI : XX2Form<60, 137,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvrspi $XT, $XB", IIC_VecFP,
|
|
[(set v4f32:$XT, (frnd v4f32:$XB))]>;
|
|
def XVRSPIC : XX2Form<60, 171,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvrspic $XT, $XB", IIC_VecFP,
|
|
[(set v4f32:$XT, (fnearbyint v4f32:$XB))]>;
|
|
def XVRSPIM : XX2Form<60, 185,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvrspim $XT, $XB", IIC_VecFP,
|
|
[(set v4f32:$XT, (ffloor v4f32:$XB))]>;
|
|
def XVRSPIP : XX2Form<60, 169,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvrspip $XT, $XB", IIC_VecFP,
|
|
[(set v4f32:$XT, (fceil v4f32:$XB))]>;
|
|
def XVRSPIZ : XX2Form<60, 153,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvrspiz $XT, $XB", IIC_VecFP,
|
|
[(set v4f32:$XT, (ftrunc v4f32:$XB))]>;
|
|
|
|
// Max/Min Instructions
|
|
let isCommutable = 1 in {
|
|
def XSMAXDP : XX3Form<60, 160,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xsmaxdp $XT, $XA, $XB", IIC_VecFP, []>;
|
|
def XSMINDP : XX3Form<60, 168,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xsmindp $XT, $XA, $XB", IIC_VecFP, []>;
|
|
|
|
def XVMAXDP : XX3Form<60, 224,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xvmaxdp $XT, $XA, $XB", IIC_VecFP, []>;
|
|
def XVMINDP : XX3Form<60, 232,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xvmindp $XT, $XA, $XB", IIC_VecFP, []>;
|
|
|
|
def XVMAXSP : XX3Form<60, 192,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xvmaxsp $XT, $XA, $XB", IIC_VecFP, []>;
|
|
def XVMINSP : XX3Form<60, 200,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xvminsp $XT, $XA, $XB", IIC_VecFP, []>;
|
|
} // isCommutable
|
|
} // Uses = [RM]
|
|
|
|
// Logical Instructions
|
|
let isCommutable = 1 in
|
|
def XXLAND : XX3Form<60, 130,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xxland $XT, $XA, $XB", IIC_VecGeneral, []>;
|
|
def XXLANDC : XX3Form<60, 138,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xxlandc $XT, $XA, $XB", IIC_VecGeneral, []>;
|
|
let isCommutable = 1 in {
|
|
def XXLNOR : XX3Form<60, 162,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xxlnor $XT, $XA, $XB", IIC_VecGeneral, []>;
|
|
def XXLOR : XX3Form<60, 146,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xxlor $XT, $XA, $XB", IIC_VecGeneral, []>;
|
|
def XXLXOR : XX3Form<60, 154,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xxlxor $XT, $XA, $XB", IIC_VecGeneral, []>;
|
|
} // isCommutable
|
|
|
|
// Permutation Instructions
|
|
def XXMRGHW : XX3Form<60, 18,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xxmrghw $XT, $XA, $XB", IIC_VecPerm, []>;
|
|
def XXMRGLW : XX3Form<60, 50,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xxmrglw $XT, $XA, $XB", IIC_VecPerm, []>;
|
|
|
|
def XXPERMDI : XX3Form_2<60, 10,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$DM),
|
|
"xxpermdi $XT, $XA, $XB, $DM", IIC_VecPerm, []>;
|
|
def XXSEL : XX4Form<60, 3,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, vsrc:$XC),
|
|
"xxsel $XT, $XA, $XB, $XC", IIC_VecPerm, []>;
|
|
|
|
def XXSLDWI : XX3Form_2<60, 2,
|
|
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$SHW),
|
|
"xxsldwi $XT, $XA, $XB, $SHW", IIC_VecPerm, []>;
|
|
def XXSPLTW : XX2Form_2<60, 164,
|
|
(outs vsrc:$XT), (ins vsrc:$XB, u2imm:$UIM),
|
|
"xxspltw $XT, $XB, $UIM", IIC_VecPerm, []>;
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} // neverHasSideEffects
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} // AddedComplexity
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def : InstAlias<"xvmovdp $XT, $XB",
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(XVCPSGNDP vsrc:$XT, vsrc:$XB, vsrc:$XB)>;
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def : InstAlias<"xvmovsp $XT, $XB",
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(XVCPSGNSP vsrc:$XT, vsrc:$XB, vsrc:$XB)>;
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def : InstAlias<"xxspltd $XT, $XB, 0",
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(XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 0)>;
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def : InstAlias<"xxspltd $XT, $XB, 1",
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(XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 3)>;
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def : InstAlias<"xxmrghd $XT, $XA, $XB",
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(XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 0)>;
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def : InstAlias<"xxmrgld $XT, $XA, $XB",
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(XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 3)>;
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def : InstAlias<"xxswapd $XT, $XB",
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(XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 2)>;
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|
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let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
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def : Pat<(v2f64 (scalar_to_vector f64:$A)),
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(INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), $A, sub_64)>;
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|
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def : Pat<(f64 (vector_extract v2f64:$S, 0)),
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(EXTRACT_SUBREG (v2f64 (COPY_TO_REGCLASS $S, VSLRC)), sub_64)>;
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def : Pat<(f64 (vector_extract v2f64:$S, 1)),
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(EXTRACT_SUBREG (v2f64 (COPY_TO_REGCLASS (XXPERMDI $S, $S, 3),
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|
VSLRC)), sub_64)>;
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|
|
|
// Additional fnmsub patterns: -a*c + b == -(a*c - b)
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|
def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
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(XSNMSUBADP $B, $C, $A)>;
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|
def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
|
|
(XSNMSUBADP $B, $C, $A)>;
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|
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def : Pat<(fma (fneg v2f64:$A), v2f64:$C, v2f64:$B),
|
|
(XVNMSUBADP $B, $C, $A)>;
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|
def : Pat<(fma v2f64:$A, (fneg v2f64:$C), v2f64:$B),
|
|
(XVNMSUBADP $B, $C, $A)>;
|
|
|
|
def : Pat<(fma (fneg v4f32:$A), v4f32:$C, v4f32:$B),
|
|
(XVNMSUBASP $B, $C, $A)>;
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|
def : Pat<(fma v4f32:$A, (fneg v4f32:$C), v4f32:$B),
|
|
(XVNMSUBASP $B, $C, $A)>;
|
|
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|
def : Pat<(v2f64 (bitconvert v4i32:$A)),
|
|
(COPY_TO_REGCLASS $A, VSRC)>;
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|
def : Pat<(v2f64 (bitconvert v8i16:$A)),
|
|
(COPY_TO_REGCLASS $A, VSRC)>;
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|
def : Pat<(v2f64 (bitconvert v16i8:$A)),
|
|
(COPY_TO_REGCLASS $A, VSRC)>;
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|
|
|
def : Pat<(v4i32 (bitconvert v2f64:$A)),
|
|
(COPY_TO_REGCLASS $A, VRRC)>;
|
|
def : Pat<(v8i16 (bitconvert v2f64:$A)),
|
|
(COPY_TO_REGCLASS $A, VRRC)>;
|
|
def : Pat<(v16i8 (bitconvert v2f64:$A)),
|
|
(COPY_TO_REGCLASS $A, VRRC)>;
|
|
|
|
} // AddedComplexity
|
|
} // HasVSX
|
|
|