Misha Brukman 8996f44f7a Fixed ordering of elements in instructions: although the binary instructions ...

list (rd, rs1, imm), in that order (bit-wise), the actual assembly syntax is
instr rd, imm, rs1, and that is how they are constructed in the instruction
selector. This fixes the discrepancy.

Also fixed some comments along the same lines and fixed page numbers referring
to where instructions are described in the Sparc manual.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6384 91177308-0d34-0410-b5e6-96231b3b80d8

2003-05-28 17:49:29 +00:00

..

CBackend

Add support for setjmp/longjmp primitives

2003-05-17 22:26:33 +00:00

SparcV9

Fixed ordering of elements in instructions: although the binary instructions

2003-05-28 17:49:29 +00:00

X86

Renamed opIsDef to opIsDefOnly.

2003-05-27 00:03:17 +00:00

Makefile

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MRegisterInfo.cpp

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TargetData.cpp

* Fix divide by zero error with empty structs

2003-05-21 18:08:44 +00:00

TargetInstrInfo.cpp

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TargetMachine.cpp

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TargetSchedInfo.cpp

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