llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-22 13:29:44 +00:00

History

Andrea Di Biagio eafdf26d89 [X86] Improved tablegen patters for matching TZCNT/LZCNT.

Teach ISel how to match a TZCNT/LZCNT from a conditional move if the
condition code is X86_COND_NE.
Existing tablegen patterns only allowed to match TZCNT/LZCNT from a
X86cond with condition code equal to X86_COND_E. To avoid introducing
extra rules, I added an 'ImmLeaf' definition that checks if the
condition code is COND_E or COND_NE.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223668 91177308-0d34-0410-b5e6-96231b3b80d8

2014-12-08 17:47:18 +00:00

Analysis

Revert a part of r223583, for now. It seems causing different emission between stage2(gcc-clang) and stage3 clang. Investigating.

2014-12-08 02:07:22 +00:00

AsmParser

IR: Add missing tests for function-local metadata

2014-12-07 17:56:16 +00:00

Bitcode

IR: Disallow function-local metadata attachments

2014-12-06 02:29:44 +00:00

CodeGen

SelectionDAG switch lowering: Replace unreachable default with most popular case.