mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-11-04 05:17:07 +00:00
b7c5bdf843
icc (#177, partial). Patch by Erick Tryzelaar. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81106 91177308-0d34-0410-b5e6-96231b3b80d8
635 lines
21 KiB
C++
635 lines
21 KiB
C++
//===- FastISelEmitter.cpp - Generate an instruction selector -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend emits code for use by the "fast" instruction
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// selection algorithm. See the comments at the top of
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// lib/CodeGen/SelectionDAG/FastISel.cpp for background.
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//
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// This file scans through the target's tablegen instruction-info files
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// and extracts instructions with obvious-looking patterns, and it emits
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// code to look up these instructions by type and operator.
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//
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//===----------------------------------------------------------------------===//
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#include "FastISelEmitter.h"
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#include "Record.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/VectorExtras.h"
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using namespace llvm;
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namespace {
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/// InstructionMemo - This class holds additional information about an
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/// instruction needed to emit code for it.
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///
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struct InstructionMemo {
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std::string Name;
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const CodeGenRegisterClass *RC;
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unsigned char SubRegNo;
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std::vector<std::string>* PhysRegs;
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};
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/// OperandsSignature - This class holds a description of a list of operand
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/// types. It has utility methods for emitting text based on the operands.
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///
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struct OperandsSignature {
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std::vector<std::string> Operands;
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bool operator<(const OperandsSignature &O) const {
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return Operands < O.Operands;
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}
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bool empty() const { return Operands.empty(); }
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/// initialize - Examine the given pattern and initialize the contents
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/// of the Operands array accordingly. Return true if all the operands
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/// are supported, false otherwise.
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///
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bool initialize(TreePatternNode *InstPatNode,
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const CodeGenTarget &Target,
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MVT::SimpleValueType VT) {
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if (!InstPatNode->isLeaf() &&
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InstPatNode->getOperator()->getName() == "imm") {
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Operands.push_back("i");
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return true;
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}
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if (!InstPatNode->isLeaf() &&
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InstPatNode->getOperator()->getName() == "fpimm") {
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Operands.push_back("f");
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return true;
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}
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const CodeGenRegisterClass *DstRC = 0;
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for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
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TreePatternNode *Op = InstPatNode->getChild(i);
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// For now, filter out any operand with a predicate.
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if (!Op->getPredicateFns().empty())
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return false;
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// For now, filter out any operand with multiple values.
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if (Op->getExtTypes().size() != 1)
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return false;
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// For now, all the operands must have the same type.
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if (Op->getTypeNum(0) != VT)
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return false;
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if (!Op->isLeaf()) {
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if (Op->getOperator()->getName() == "imm") {
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Operands.push_back("i");
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continue;
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}
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if (Op->getOperator()->getName() == "fpimm") {
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Operands.push_back("f");
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continue;
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}
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// For now, ignore other non-leaf nodes.
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return false;
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}
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DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue());
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if (!OpDI)
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return false;
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Record *OpLeafRec = OpDI->getDef();
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// For now, the only other thing we accept is register operands.
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const CodeGenRegisterClass *RC = 0;
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if (OpLeafRec->isSubClassOf("RegisterClass"))
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RC = &Target.getRegisterClass(OpLeafRec);
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else if (OpLeafRec->isSubClassOf("Register"))
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RC = Target.getRegisterClassForRegister(OpLeafRec);
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else
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return false;
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// For now, require the register operands' register classes to all
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// be the same.
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if (!RC)
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return false;
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// For now, all the operands must have the same register class.
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if (DstRC) {
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if (DstRC != RC)
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return false;
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} else
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DstRC = RC;
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Operands.push_back("r");
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}
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return true;
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}
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void PrintParameters(raw_ostream &OS) const {
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for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
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if (Operands[i] == "r") {
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OS << "unsigned Op" << i;
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} else if (Operands[i] == "i") {
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OS << "uint64_t imm" << i;
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} else if (Operands[i] == "f") {
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OS << "ConstantFP *f" << i;
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} else {
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assert("Unknown operand kind!");
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abort();
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}
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if (i + 1 != e)
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OS << ", ";
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}
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}
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void PrintArguments(raw_ostream &OS,
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const std::vector<std::string>& PR) const {
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assert(PR.size() == Operands.size());
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bool PrintedArg = false;
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for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
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if (PR[i] != "")
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// Implicit physical register operand.
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continue;
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if (PrintedArg)
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OS << ", ";
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if (Operands[i] == "r") {
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OS << "Op" << i;
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PrintedArg = true;
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} else if (Operands[i] == "i") {
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OS << "imm" << i;
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PrintedArg = true;
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} else if (Operands[i] == "f") {
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OS << "f" << i;
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PrintedArg = true;
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} else {
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assert("Unknown operand kind!");
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abort();
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}
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}
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}
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void PrintArguments(raw_ostream &OS) const {
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for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
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if (Operands[i] == "r") {
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OS << "Op" << i;
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} else if (Operands[i] == "i") {
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OS << "imm" << i;
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} else if (Operands[i] == "f") {
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OS << "f" << i;
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} else {
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assert("Unknown operand kind!");
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abort();
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}
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if (i + 1 != e)
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OS << ", ";
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}
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}
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void PrintManglingSuffix(raw_ostream &OS,
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const std::vector<std::string>& PR) const {
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for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
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if (PR[i] != "")
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// Implicit physical register operand. e.g. Instruction::Mul expect to
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// select to a binary op. On x86, mul may take a single operand with
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// the other operand being implicit. We must emit something that looks
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// like a binary instruction except for the very inner FastEmitInst_*
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// call.
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continue;
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OS << Operands[i];
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}
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}
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void PrintManglingSuffix(raw_ostream &OS) const {
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for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
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OS << Operands[i];
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}
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}
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};
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class FastISelMap {
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typedef std::map<std::string, InstructionMemo> PredMap;
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typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap;
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typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap;
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typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap;
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typedef std::map<OperandsSignature, OpcodeTypeRetPredMap> OperandsOpcodeTypeRetPredMap;
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OperandsOpcodeTypeRetPredMap SimplePatterns;
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std::string InstNS;
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public:
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explicit FastISelMap(std::string InstNS);
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void CollectPatterns(CodeGenDAGPatterns &CGP);
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void PrintFunctionDefinitions(raw_ostream &OS);
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};
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}
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static std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) {
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return CGP.getSDNodeInfo(Op).getEnumName();
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}
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static std::string getLegalCName(std::string OpName) {
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std::string::size_type pos = OpName.find("::");
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if (pos != std::string::npos)
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OpName.replace(pos, 2, "_");
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return OpName;
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}
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FastISelMap::FastISelMap(std::string instns)
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: InstNS(instns) {
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}
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void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) {
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const CodeGenTarget &Target = CGP.getTargetInfo();
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// Determine the target's namespace name.
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InstNS = Target.getInstNamespace() + "::";
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assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
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// Scan through all the patterns and record the simple ones.
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for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(),
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E = CGP.ptm_end(); I != E; ++I) {
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const PatternToMatch &Pattern = *I;
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// For now, just look at Instructions, so that we don't have to worry
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// about emitting multiple instructions for a pattern.
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TreePatternNode *Dst = Pattern.getDstPattern();
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if (Dst->isLeaf()) continue;
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Record *Op = Dst->getOperator();
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if (!Op->isSubClassOf("Instruction"))
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continue;
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CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op->getName());
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if (II.OperandList.empty())
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continue;
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// For now, ignore multi-instruction patterns.
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bool MultiInsts = false;
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for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) {
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TreePatternNode *ChildOp = Dst->getChild(i);
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if (ChildOp->isLeaf())
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continue;
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if (ChildOp->getOperator()->isSubClassOf("Instruction")) {
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MultiInsts = true;
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break;
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}
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}
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if (MultiInsts)
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continue;
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// For now, ignore instructions where the first operand is not an
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// output register.
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const CodeGenRegisterClass *DstRC = 0;
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unsigned SubRegNo = ~0;
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if (Op->getName() != "EXTRACT_SUBREG") {
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Record *Op0Rec = II.OperandList[0].Rec;
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if (!Op0Rec->isSubClassOf("RegisterClass"))
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continue;
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DstRC = &Target.getRegisterClass(Op0Rec);
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if (!DstRC)
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continue;
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} else {
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SubRegNo = static_cast<IntInit*>(
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Dst->getChild(1)->getLeafValue())->getValue();
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}
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// Inspect the pattern.
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TreePatternNode *InstPatNode = Pattern.getSrcPattern();
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if (!InstPatNode) continue;
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if (InstPatNode->isLeaf()) continue;
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Record *InstPatOp = InstPatNode->getOperator();
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std::string OpcodeName = getOpcodeName(InstPatOp, CGP);
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MVT::SimpleValueType RetVT = InstPatNode->getTypeNum(0);
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MVT::SimpleValueType VT = RetVT;
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if (InstPatNode->getNumChildren())
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VT = InstPatNode->getChild(0)->getTypeNum(0);
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// For now, filter out instructions which just set a register to
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// an Operand or an immediate, like MOV32ri.
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if (InstPatOp->isSubClassOf("Operand"))
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continue;
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// For now, filter out any instructions with predicates.
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if (!InstPatNode->getPredicateFns().empty())
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continue;
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// Check all the operands.
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OperandsSignature Operands;
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if (!Operands.initialize(InstPatNode, Target, VT))
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continue;
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std::vector<std::string>* PhysRegInputs = new std::vector<std::string>();
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if (!InstPatNode->isLeaf() &&
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(InstPatNode->getOperator()->getName() == "imm" ||
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InstPatNode->getOperator()->getName() == "fpimmm"))
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PhysRegInputs->push_back("");
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else if (!InstPatNode->isLeaf()) {
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for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
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TreePatternNode *Op = InstPatNode->getChild(i);
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if (!Op->isLeaf()) {
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PhysRegInputs->push_back("");
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continue;
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}
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DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue());
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Record *OpLeafRec = OpDI->getDef();
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std::string PhysReg;
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if (OpLeafRec->isSubClassOf("Register")) {
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PhysReg += static_cast<StringInit*>(OpLeafRec->getValue( \
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"Namespace")->getValue())->getValue();
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PhysReg += "::";
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std::vector<CodeGenRegister> Regs = Target.getRegisters();
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for (unsigned i = 0; i < Regs.size(); ++i) {
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if (Regs[i].TheDef == OpLeafRec) {
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PhysReg += Regs[i].getName();
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break;
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}
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}
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}
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PhysRegInputs->push_back(PhysReg);
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}
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} else
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PhysRegInputs->push_back("");
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// Get the predicate that guards this pattern.
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std::string PredicateCheck = Pattern.getPredicateCheck();
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// Ok, we found a pattern that we can handle. Remember it.
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InstructionMemo Memo = {
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Pattern.getDstPattern()->getOperator()->getName(),
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DstRC,
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SubRegNo,
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PhysRegInputs
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};
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assert(!SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck) &&
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"Duplicate pattern!");
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SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo;
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}
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}
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void FastISelMap::PrintFunctionDefinitions(raw_ostream &OS) {
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// Now emit code for all the patterns that we collected.
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for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(),
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OE = SimplePatterns.end(); OI != OE; ++OI) {
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const OperandsSignature &Operands = OI->first;
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const OpcodeTypeRetPredMap &OTM = OI->second;
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for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
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I != E; ++I) {
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const std::string &Opcode = I->first;
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const TypeRetPredMap &TM = I->second;
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OS << "// FastEmit functions for " << Opcode << ".\n";
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OS << "\n";
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// Emit one function for each opcode,type pair.
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for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
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TI != TE; ++TI) {
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MVT::SimpleValueType VT = TI->first;
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const RetPredMap &RM = TI->second;
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if (RM.size() != 1) {
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for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
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RI != RE; ++RI) {
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MVT::SimpleValueType RetVT = RI->first;
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const PredMap &PM = RI->second;
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bool HasPred = false;
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OS << "unsigned FastEmit_"
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<< getLegalCName(Opcode)
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<< "_" << getLegalCName(getName(VT))
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<< "_" << getLegalCName(getName(RetVT)) << "_";
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Operands.PrintManglingSuffix(OS);
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OS << "(";
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Operands.PrintParameters(OS);
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OS << ") {\n";
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// Emit code for each possible instruction. There may be
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// multiple if there are subtarget concerns.
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for (PredMap::const_iterator PI = PM.begin(), PE = PM.end();
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PI != PE; ++PI) {
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std::string PredicateCheck = PI->first;
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const InstructionMemo &Memo = PI->second;
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if (PredicateCheck.empty()) {
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assert(!HasPred &&
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"Multiple instructions match, at least one has "
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"a predicate and at least one doesn't!");
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} else {
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OS << " if (" + PredicateCheck + ") {\n";
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OS << " ";
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HasPred = true;
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}
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for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
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if ((*Memo.PhysRegs)[i] != "")
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OS << " TII.copyRegToReg(*MBB, MBB->end(), "
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<< (*Memo.PhysRegs)[i] << ", Op" << i << ", "
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<< "TM.getRegisterInfo()->getPhysicalRegisterRegClass("
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<< (*Memo.PhysRegs)[i] << "), "
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<< "MRI.getRegClass(Op" << i << "));\n";
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}
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OS << " return FastEmitInst_";
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if (Memo.SubRegNo == (unsigned char)~0) {
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Operands.PrintManglingSuffix(OS, *Memo.PhysRegs);
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OS << "(" << InstNS << Memo.Name << ", ";
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OS << InstNS << Memo.RC->getName() << "RegisterClass";
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if (!Operands.empty())
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OS << ", ";
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Operands.PrintArguments(OS, *Memo.PhysRegs);
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OS << ");\n";
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} else {
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OS << "extractsubreg(" << getName(RetVT);
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OS << ", Op0, ";
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OS << (unsigned)Memo.SubRegNo;
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OS << ");\n";
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}
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if (HasPred)
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OS << " }\n";
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}
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// Return 0 if none of the predicates were satisfied.
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if (HasPred)
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OS << " return 0;\n";
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OS << "}\n";
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OS << "\n";
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}
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// Emit one function for the type that demultiplexes on return type.
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OS << "unsigned FastEmit_"
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<< getLegalCName(Opcode) << "_"
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<< getLegalCName(getName(VT)) << "_";
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Operands.PrintManglingSuffix(OS);
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OS << "(MVT RetVT";
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if (!Operands.empty())
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OS << ", ";
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Operands.PrintParameters(OS);
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OS << ") {\nswitch (RetVT.SimpleTy) {\n";
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for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
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RI != RE; ++RI) {
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MVT::SimpleValueType RetVT = RI->first;
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OS << " case " << getName(RetVT) << ": return FastEmit_"
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<< getLegalCName(Opcode) << "_" << getLegalCName(getName(VT))
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<< "_" << getLegalCName(getName(RetVT)) << "_";
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Operands.PrintManglingSuffix(OS);
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OS << "(";
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Operands.PrintArguments(OS);
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OS << ");\n";
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}
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OS << " default: return 0;\n}\n}\n\n";
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} else {
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// Non-variadic return type.
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OS << "unsigned FastEmit_"
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<< getLegalCName(Opcode) << "_"
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<< getLegalCName(getName(VT)) << "_";
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Operands.PrintManglingSuffix(OS);
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OS << "(MVT RetVT";
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if (!Operands.empty())
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OS << ", ";
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Operands.PrintParameters(OS);
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OS << ") {\n";
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OS << " if (RetVT.SimpleTy != " << getName(RM.begin()->first)
|
|
<< ")\n return 0;\n";
|
|
|
|
const PredMap &PM = RM.begin()->second;
|
|
bool HasPred = false;
|
|
|
|
// Emit code for each possible instruction. There may be
|
|
// multiple if there are subtarget concerns.
|
|
for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE;
|
|
++PI) {
|
|
std::string PredicateCheck = PI->first;
|
|
const InstructionMemo &Memo = PI->second;
|
|
|
|
if (PredicateCheck.empty()) {
|
|
assert(!HasPred &&
|
|
"Multiple instructions match, at least one has "
|
|
"a predicate and at least one doesn't!");
|
|
} else {
|
|
OS << " if (" + PredicateCheck + ") {\n";
|
|
OS << " ";
|
|
HasPred = true;
|
|
}
|
|
|
|
for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
|
|
if ((*Memo.PhysRegs)[i] != "")
|
|
OS << " TII.copyRegToReg(*MBB, MBB->end(), "
|
|
<< (*Memo.PhysRegs)[i] << ", Op" << i << ", "
|
|
<< "TM.getRegisterInfo()->getPhysicalRegisterRegClass("
|
|
<< (*Memo.PhysRegs)[i] << "), "
|
|
<< "MRI.getRegClass(Op" << i << "));\n";
|
|
}
|
|
|
|
OS << " return FastEmitInst_";
|
|
|
|
if (Memo.SubRegNo == (unsigned char)~0) {
|
|
Operands.PrintManglingSuffix(OS, *Memo.PhysRegs);
|
|
OS << "(" << InstNS << Memo.Name << ", ";
|
|
OS << InstNS << Memo.RC->getName() << "RegisterClass";
|
|
if (!Operands.empty())
|
|
OS << ", ";
|
|
Operands.PrintArguments(OS, *Memo.PhysRegs);
|
|
OS << ");\n";
|
|
} else {
|
|
OS << "extractsubreg(RetVT, Op0, ";
|
|
OS << (unsigned)Memo.SubRegNo;
|
|
OS << ");\n";
|
|
}
|
|
|
|
if (HasPred)
|
|
OS << " }\n";
|
|
}
|
|
|
|
// Return 0 if none of the predicates were satisfied.
|
|
if (HasPred)
|
|
OS << " return 0;\n";
|
|
OS << "}\n";
|
|
OS << "\n";
|
|
}
|
|
}
|
|
|
|
// Emit one function for the opcode that demultiplexes based on the type.
|
|
OS << "unsigned FastEmit_"
|
|
<< getLegalCName(Opcode) << "_";
|
|
Operands.PrintManglingSuffix(OS);
|
|
OS << "(MVT VT, MVT RetVT";
|
|
if (!Operands.empty())
|
|
OS << ", ";
|
|
Operands.PrintParameters(OS);
|
|
OS << ") {\n";
|
|
OS << " switch (VT.SimpleTy) {\n";
|
|
for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
|
|
TI != TE; ++TI) {
|
|
MVT::SimpleValueType VT = TI->first;
|
|
std::string TypeName = getName(VT);
|
|
OS << " case " << TypeName << ": return FastEmit_"
|
|
<< getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_";
|
|
Operands.PrintManglingSuffix(OS);
|
|
OS << "(RetVT";
|
|
if (!Operands.empty())
|
|
OS << ", ";
|
|
Operands.PrintArguments(OS);
|
|
OS << ");\n";
|
|
}
|
|
OS << " default: return 0;\n";
|
|
OS << " }\n";
|
|
OS << "}\n";
|
|
OS << "\n";
|
|
}
|
|
|
|
OS << "// Top-level FastEmit function.\n";
|
|
OS << "\n";
|
|
|
|
// Emit one function for the operand signature that demultiplexes based
|
|
// on opcode and type.
|
|
OS << "unsigned FastEmit_";
|
|
Operands.PrintManglingSuffix(OS);
|
|
OS << "(MVT VT, MVT RetVT, ISD::NodeType Opcode";
|
|
if (!Operands.empty())
|
|
OS << ", ";
|
|
Operands.PrintParameters(OS);
|
|
OS << ") {\n";
|
|
OS << " switch (Opcode) {\n";
|
|
for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
|
|
I != E; ++I) {
|
|
const std::string &Opcode = I->first;
|
|
|
|
OS << " case " << Opcode << ": return FastEmit_"
|
|
<< getLegalCName(Opcode) << "_";
|
|
Operands.PrintManglingSuffix(OS);
|
|
OS << "(VT, RetVT";
|
|
if (!Operands.empty())
|
|
OS << ", ";
|
|
Operands.PrintArguments(OS);
|
|
OS << ");\n";
|
|
}
|
|
OS << " default: return 0;\n";
|
|
OS << " }\n";
|
|
OS << "}\n";
|
|
OS << "\n";
|
|
}
|
|
}
|
|
|
|
void FastISelEmitter::run(raw_ostream &OS) {
|
|
const CodeGenTarget &Target = CGP.getTargetInfo();
|
|
|
|
// Determine the target's namespace name.
|
|
std::string InstNS = Target.getInstNamespace() + "::";
|
|
assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
|
|
|
|
EmitSourceFileHeader("\"Fast\" Instruction Selector for the " +
|
|
Target.getName() + " target", OS);
|
|
|
|
FastISelMap F(InstNS);
|
|
F.CollectPatterns(CGP);
|
|
F.PrintFunctionDefinitions(OS);
|
|
}
|
|
|
|
FastISelEmitter::FastISelEmitter(RecordKeeper &R)
|
|
: Records(R),
|
|
CGP(R) {
|
|
}
|
|
|