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a1719c9130
Add ISel::visitShiftInst() to instruction select shift instructions. Add a comment in visitAdd about how to do 64 bit adds. X86InstrInfo.def: Add register-to-register move opcodes and shift opcodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4477 91177308-0d34-0410-b5e6-96231b3b80d8
361 lines
10 KiB
C++
361 lines
10 KiB
C++
//===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
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//
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// This file defines a simple peephole instruction selector for the x86 platform
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "llvm/Function.h"
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#include "llvm/iTerminators.h"
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#include "llvm/iOther.h"
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#include "llvm/Type.h"
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#include "llvm/Constants.h"
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#include "llvm/Pass.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Support/InstVisitor.h"
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#include <map>
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namespace {
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struct ISel : public FunctionPass, InstVisitor<ISel> {
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TargetMachine &TM;
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MachineFunction *F; // The function we are compiling into
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MachineBasicBlock *BB; // The current MBB we are compiling
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unsigned CurReg;
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std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
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ISel(TargetMachine &tm)
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: TM(tm), F(0), BB(0), CurReg(MRegisterInfo::FirstVirtualRegister) {}
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/// runOnFunction - Top level implementation of instruction selection for
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/// the entire function.
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///
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bool runOnFunction(Function &Fn) {
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F = &MachineFunction::construct(&Fn, TM);
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visit(Fn);
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RegMap.clear();
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F = 0;
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return false; // We never modify the LLVM itself.
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}
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/// visitBasicBlock - This method is called when we are visiting a new basic
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/// block. This simply creates a new MachineBasicBlock to emit code into
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/// and adds it to the current MachineFunction. Subsequent visit* for
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/// instructions will be invoked for all instructions in the basic block.
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///
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void visitBasicBlock(BasicBlock &LLVM_BB) {
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BB = new MachineBasicBlock(&LLVM_BB);
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// FIXME: Use the auto-insert form when it's available
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F->getBasicBlockList().push_back(BB);
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}
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// Visitation methods for various instructions. These methods simply emit
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// fixed X86 code for each instruction.
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//
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void visitReturnInst(ReturnInst &RI);
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void visitAdd(BinaryOperator &B);
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void visitShiftInst(ShiftInst &I);
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void visitInstruction(Instruction &I) {
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std::cerr << "Cannot instruction select: " << I;
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abort();
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}
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/// copyConstantToRegister - Output the instructions required to put the
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/// specified constant into the specified register.
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///
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void copyConstantToRegister(Constant *C, unsigned Reg);
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/// getReg - This method turns an LLVM value into a register number. This
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/// is guaranteed to produce the same register number for a particular value
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/// every time it is queried.
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///
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unsigned getReg(Value &V) { return getReg(&V); } // Allow references
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unsigned getReg(Value *V) {
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unsigned &Reg = RegMap[V];
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if (Reg == 0)
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Reg = CurReg++;
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// If this operand is a constant, emit the code to copy the constant into
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// the register here...
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//
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if (Constant *C = dyn_cast<Constant>(V))
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copyConstantToRegister(C, Reg);
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return Reg;
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}
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};
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}
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/// copyConstantToRegister - Output the instructions required to put the
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/// specified constant into the specified register.
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///
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void ISel::copyConstantToRegister(Constant *C, unsigned R) {
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assert (!isa<ConstantExpr>(C) && "Constant expressions not yet handled!\n");
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switch (C->getType()->getPrimitiveID()) {
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case Type::SByteTyID:
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BuildMI(BB, X86::MOVir8, 1, R).addSImm(cast<ConstantSInt>(C)->getValue());
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break;
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case Type::UByteTyID:
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BuildMI(BB, X86::MOVir8, 1, R).addZImm(cast<ConstantUInt>(C)->getValue());
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break;
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case Type::ShortTyID:
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BuildMI(BB, X86::MOVir16, 1, R).addSImm(cast<ConstantSInt>(C)->getValue());
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break;
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case Type::UShortTyID:
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BuildMI(BB, X86::MOVir16, 1, R).addZImm(cast<ConstantUInt>(C)->getValue());
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break;
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case Type::IntTyID:
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BuildMI(BB, X86::MOVir32, 1, R).addSImm(cast<ConstantSInt>(C)->getValue());
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break;
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case Type::UIntTyID:
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BuildMI(BB, X86::MOVir32, 1, R).addZImm(cast<ConstantUInt>(C)->getValue());
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break;
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default: assert(0 && "Type not handled yet!");
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}
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}
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/// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
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/// we have the following possibilities:
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///
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/// ret void: No return value, simply emit a 'ret' instruction
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/// ret sbyte, ubyte : Extend value into EAX and return
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/// ret short, ushort: Extend value into EAX and return
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/// ret int, uint : Move value into EAX and return
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/// ret pointer : Move value into EAX and return
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/// ret long, ulong : Move value into EAX/EDX (?) and return
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/// ret float/double : ? Top of FP stack? XMM0?
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///
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void ISel::visitReturnInst(ReturnInst &I) {
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if (I.getNumOperands() != 0) { // Not 'ret void'?
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// Move result into a hard register... then emit a ret
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visitInstruction(I); // abort
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}
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// Emit a simple 'ret' instruction... appending it to the end of the basic
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// block
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BuildMI(BB, X86::RET, 0);
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}
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/// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
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/// for constant immediate shift values, and for constant immediate
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/// shift values equal to 1. Even the general case is sort of special,
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/// because the shift amount has to be in CL, not just any old register.
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///
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void
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ISel::visitShiftInst (ShiftInst & I)
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{
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unsigned Op0r = getReg (I.getOperand (0));
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unsigned DestReg = getReg (I);
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unsigned operandSize = I.getOperand (0)->getType ()->getPrimitiveSize ();
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bool isRightShift = (I.getOpcode () == Instruction::Shr);
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bool isOperandUnsigned = I.getType ()->isUnsigned ();
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bool isConstantShiftAmount = (isa <ConstantUInt> (I.getOperand (1)));
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if (ConstantUInt *CUI = dyn_cast <ConstantUInt> (I.getOperand (1)))
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{
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// The shift amount is constant. Get its value.
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uint64_t shAmt = CUI->getValue ();
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// Emit: <insn> reg, shamt (shift-by-immediate opcode "ir" form.)
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if (isRightShift)
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{
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if (isOperandUnsigned)
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{
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// This is a shift right logical (SHR).
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switch (operandSize)
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{
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case 1:
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BuildMI (BB, X86::SHRir8, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 2:
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BuildMI (BB, X86::SHRir16, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 4:
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BuildMI (BB, X86::SHRir32, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 8:
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default:
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visitInstruction (I);
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break;
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}
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}
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else
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{
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// This is a shift right arithmetic (SAR).
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switch (operandSize)
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{
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case 1:
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BuildMI (BB, X86::SARir8, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 2:
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BuildMI (BB, X86::SARir16, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 4:
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BuildMI (BB, X86::SARir32, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 8:
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default:
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visitInstruction (I);
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break;
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}
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}
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}
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else
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{
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// This is a left shift (SHL).
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switch (operandSize)
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{
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case 1:
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BuildMI (BB, X86::SHLir8, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 2:
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BuildMI (BB, X86::SHLir16, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 4:
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BuildMI (BB, X86::SHLir32, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 8:
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default:
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visitInstruction (I);
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break;
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}
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}
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}
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else
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{
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// The shift amount is non-constant.
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//
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// In fact, you can only shift with a variable shift amount if
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// that amount is already in the CL register, so we have to put it
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// there first.
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//
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// Get it from the register it's in.
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unsigned Op1r = getReg (I.getOperand (1));
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// Emit: move cl, shiftAmount (put the shift amount in CL.)
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BuildMI (BB, X86::MOVrr8, 2, X86::CL).addReg (Op1r);
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// Emit: <insn> reg, cl (shift-by-CL opcode; "rr" form.)
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if (isRightShift)
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{
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if (isOperandUnsigned)
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{
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// This is a shift right logical (SHR).
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switch (operandSize)
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{
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case 1:
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BuildMI (BB, X86::SHRrr8, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 2:
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BuildMI (BB, X86::SHRrr16, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 4:
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BuildMI (BB, X86::SHRrr32, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 8:
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default:
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visitInstruction (I);
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break;
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}
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}
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else
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{
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// This is a shift right arithmetic (SAR).
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switch (operandSize)
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{
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case 1:
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BuildMI (BB, X86::SARrr8, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 2:
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BuildMI (BB, X86::SARrr16, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 4:
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BuildMI (BB, X86::SARrr32, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 8:
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default:
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visitInstruction (I);
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break;
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}
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}
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}
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else
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{
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// This is a left shift (SHL).
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switch (operandSize)
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{
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case 1:
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BuildMI (BB, X86::SHLrr8, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 2:
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BuildMI (BB, X86::SHLrr16, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 4:
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BuildMI (BB, X86::SHLrr32, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 8:
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default:
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visitInstruction (I);
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break;
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}
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}
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}
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}
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/// 'add' instruction - Simply turn this into an x86 reg,reg add instruction.
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void ISel::visitAdd(BinaryOperator &B) {
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unsigned Op0r = getReg(B.getOperand(0)), Op1r = getReg(B.getOperand(1));
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unsigned DestReg = getReg(B);
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switch (B.getType()->getPrimitiveSize()) {
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case 1: // UByte, SByte
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BuildMI(BB, X86::ADDrr8, 2, DestReg).addReg(Op0r).addReg(Op1r);
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break;
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case 2: // UShort, Short
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BuildMI(BB, X86::ADDrr16, 2, DestReg).addReg(Op0r).addReg(Op1r);
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break;
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case 4: // UInt, Int
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BuildMI(BB, X86::ADDrr32, 2, DestReg).addReg(Op0r).addReg(Op1r);
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break;
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case 8: // ULong, Long
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// Here we have a pair of operands each occupying a pair of registers.
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// We need to do an ADDrr32 of the least-significant pair immediately
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// followed by an ADCrr32 (Add with Carry) of the most-significant pair.
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// I don't know how we are representing these multi-register arguments.
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default:
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visitInstruction(B); // abort
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}
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}
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/// createSimpleX86InstructionSelector - This pass converts an LLVM function
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/// into a machine code representation is a very simple peep-hole fashion. The
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/// generated code sucks but the implementation is nice and simple.
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///
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Pass *createSimpleX86InstructionSelector(TargetMachine &TM) {
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return new ISel(TM);
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}
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