Files
llvm-6502/lib/CodeGen/SelectionDAG
Owen Anderson ec6d4d8afb Fix issues with ISD::FNEG and ISD::FMA SDNodes where they would not be constant-folded
during DAGCombine in certain circumstances.  Unfortunately, the circumstances required
to trigger the issue seem to require a pretty specific interaction of DAGCombines,
and I haven't been able to find a testcase that reproduces on X86, ARM, or AArch64.
The functionality added here is replicated in essentially every other DAG combine,
so it seems pretty obviously correct.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214622 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-02 08:45:33 +00:00
..
2014-07-23 22:34:13 +00:00
2014-07-14 18:21:07 +00:00