mirror of
				https://github.com/c64scene-ar/llvm-6502.git
				synced 2025-11-04 05:17:07 +00:00 
			
		
		
		
	Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
		
	
		
			
				
	
	
		
			27 lines
		
	
	
		
			977 B
		
	
	
	
		
			LLVM
		
	
	
	
	
	
			
		
		
	
	
			27 lines
		
	
	
		
			977 B
		
	
	
	
		
			LLVM
		
	
	
	
	
	
; RUN: llc < %s -march=x86-64 -mattr=+sse4.1
 | 
						|
 | 
						|
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 | 
						|
target triple = "x86_64-apple-darwin11.0.0"
 | 
						|
 | 
						|
define i64 @__builtin_ia32_vec_ext_v2di(<2 x i64> %a, i32 %i) nounwind {
 | 
						|
  %1 = alloca <2 x i64>, align 16
 | 
						|
  %2 = alloca i32, align 4
 | 
						|
  store <2 x i64> %a, <2 x i64>* %1, align 16
 | 
						|
  store i32 %i, i32* %2, align 4
 | 
						|
  %3 = load <2 x i64>, <2 x i64>* %1, align 16
 | 
						|
  %4 = load i32, i32* %2, align 4
 | 
						|
  %5 = extractelement <2 x i64> %3, i32 %4
 | 
						|
  ret i64 %5
 | 
						|
}
 | 
						|
 | 
						|
define <2 x i64> @__builtin_ia32_vec_int_v2di(<2 x i64> %a, i32 %i) nounwind {
 | 
						|
  %1 = alloca <2 x i64>, align 16
 | 
						|
  %2 = alloca i32, align 4
 | 
						|
  store <2 x i64> %a, <2 x i64>* %1, align 16
 | 
						|
  store i32 %i, i32* %2, align 4
 | 
						|
  %3 = load <2 x i64>, <2 x i64>* %1, align 16
 | 
						|
  %4 = load i32, i32* %2, align 4
 | 
						|
  %5 = insertelement <2 x i64> %3, i64 1, i32 %4
 | 
						|
  ret <2 x i64> %5
 | 
						|
}
 |