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llvm-6502/lib/Target/R600
History
Vincent Lejeune 81c5d11c25 R600: Rewrite an awkward loop in R600MachineScheduler 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183458 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 23:08:32 +00:00
..
InstPrinter
Move passes from namespace llvm into anonymous namespaces. Sort includes while there.
2013-05-23 17:10:37 +00:00
MCTargetDesc
R600: Hide symbols of implementation details.
2013-05-23 15:43:05 +00:00
TargetInfo
…
AMDGPU.h
R600: Add a pass that merge Vector Register
2013-06-05 21:38:04 +00:00
AMDGPU.td
…
AMDGPUAsmPrinter.cpp
Move passes from namespace llvm into anonymous namespaces. Sort includes while there.
2013-05-23 17:10:37 +00:00
AMDGPUAsmPrinter.h
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AMDGPUCallingConv.td
R600/SI: Add a calling convention for compute shaders
2013-06-03 17:40:11 +00:00
AMDGPUConvertToISA.cpp
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AMDGPUFrameLowering.cpp
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AMDGPUFrameLowering.h
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AMDGPUIndirectAddressing.cpp
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AMDGPUInstrInfo.cpp
R600: Hide symbols of implementation details.
2013-05-23 15:43:05 +00:00
AMDGPUInstrInfo.h
…
AMDGPUInstrInfo.td
Create an FPOW SDNode opcode def in the target independent .td file rather than in a specific backend.
2013-05-22 06:36:09 +00:00
AMDGPUInstructions.td
R600/SI: Add support for global loads
2013-06-03 17:39:43 +00:00
AMDGPUIntrinsics.td
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AMDGPUISelLowering.cpp
R600/SI: Add a calling convention for compute shaders
2013-06-03 17:40:11 +00:00
AMDGPUISelLowering.h
R600/SI: Add support for work item and work group intrinsics
2013-06-03 17:40:18 +00:00
AMDGPUMachineFunction.cpp
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AMDGPUMachineFunction.h
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AMDGPUMCInstLower.cpp
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AMDGPUMCInstLower.h
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AMDGPURegisterInfo.cpp
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AMDGPURegisterInfo.h
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AMDGPURegisterInfo.td
Make SubRegIndex size mandatory, following r183020.
2013-05-31 23:45:26 +00:00
AMDGPUStructurizeCFG.cpp
Silencing an MSVC warning about mixing bool and unsigned int.
2013-06-04 01:03:03 +00:00
AMDGPUSubtarget.cpp
Temporary fix to get rid of gcc warning.
2013-05-29 07:32:08 +00:00
AMDGPUSubtarget.h
R600: Factorize Fetch size limit inside AMDGPUSubTarget
2013-05-17 16:49:55 +00:00
AMDGPUTargetMachine.cpp
R600: Add a pass that merge Vector Register
2013-06-05 21:38:04 +00:00
AMDGPUTargetMachine.h
Fix a leak on the r600 backend.
2013-05-23 03:31:47 +00:00
AMDIL7XXDevice.cpp
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AMDIL7XXDevice.h
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AMDIL.h
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AMDILBase.td
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AMDILCFGStructurizer.cpp
R600: Hide symbols of implementation details.
2013-05-23 15:43:05 +00:00
AMDILDevice.cpp
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AMDILDevice.h
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AMDILDeviceInfo.cpp
R600/SI: Add processor type for Hainan asic
2013-05-14 14:42:56 +00:00
AMDILDeviceInfo.h
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AMDILDevices.h
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AMDILEvergreenDevice.cpp
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AMDILEvergreenDevice.h
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AMDILInstrInfo.td
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AMDILIntrinsicInfo.cpp
Check that a function starts with llvm. before using GET_FUNCTION_RECOGNIZER.
2013-05-22 14:57:42 +00:00
AMDILIntrinsicInfo.h
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AMDILIntrinsics.td
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AMDILISelDAGToDAG.cpp
Cast to the proper type.
2013-06-06 01:04:21 +00:00
AMDILISelLowering.cpp
Track IR ordering of SelectionDAG nodes 2/4.
2013-05-25 02:42:55 +00:00
AMDILNIDevice.cpp
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AMDILNIDevice.h
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AMDILRegisterInfo.td
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AMDILSIDevice.cpp
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AMDILSIDevice.h
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CMakeLists.txt
R600: Add a pass that merge Vector Register
2013-06-05 21:38:04 +00:00
LLVMBuild.txt
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Makefile
…
Processors.td
R600/SI: Add processor type for Hainan asic
2013-05-14 14:42:56 +00:00
R600ControlFlowFinalizer.cpp
R600: CALL_FS consumes a stack size entry
2013-06-03 15:44:42 +00:00
R600Defines.h
R600: Relax some vector constraints on Dot4.
2013-05-17 16:50:32 +00:00
R600EmitClauseMarkers.cpp
R600: Const/Neg/Abs can be folded to dot4
2013-06-04 23:17:15 +00:00
R600ExpandSpecialInstrs.cpp
R600: Const/Neg/Abs can be folded to dot4
2013-06-04 23:17:15 +00:00
R600InstrInfo.cpp
R600: Make sure to schedule AR register uses and defs in the same clause
2013-06-05 03:43:06 +00:00
R600InstrInfo.h
R600: Const/Neg/Abs can be folded to dot4
2013-06-04 23:17:15 +00:00
R600Instructions.td
R600: Constraints input regs of interp_xy,_zw
2013-06-03 15:44:16 +00:00
R600Intrinsics.td
R600: Improve texture handling
2013-05-17 16:50:20 +00:00
R600ISelLowering.cpp
R600: Swizzle texture/export instructions
2013-06-04 15:04:53 +00:00
R600ISelLowering.h
R600: Swizzle texture/export instructions
2013-06-04 15:04:53 +00:00
R600MachineFunctionInfo.cpp
…
R600MachineFunctionInfo.h
Move passes from namespace llvm into anonymous namespaces. Sort includes while there.
2013-05-23 17:10:37 +00:00
R600MachineScheduler.cpp
R600: Remove leftover code in R600MachineScheduler.cpp
2013-06-06 14:18:29 +00:00
R600MachineScheduler.h
R600: Schedule copy from phys register at beginning of block
2013-06-05 20:27:35 +00:00
R600OptimizeVectorRegisters.cpp
R600: Rewrite an awkward loop in R600MachineScheduler
2013-06-06 23:08:32 +00:00
R600Packetizer.cpp
R600: 3 op instructions have no write bit but the result are store in PV
2013-06-03 15:56:12 +00:00
R600RegisterInfo.cpp
R600: Use bottom up scheduling algorithm
2013-05-17 16:50:56 +00:00
R600RegisterInfo.h
R600: Use bottom up scheduling algorithm
2013-05-17 16:50:56 +00:00
R600RegisterInfo.td
R600: use capital letter for PV channel
2013-06-03 15:44:35 +00:00
R600Schedule.td
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R600TextureIntrinsicsReplacer.cpp
Move passes from namespace llvm into anonymous namespaces. Sort includes while there.
2013-05-23 17:10:37 +00:00
SIAnnotateControlFlow.cpp
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SIDefines.h
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SIInsertWaits.cpp
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SIInstrFormats.td
R600/SI: Use the same names for VOP3 operands and encoding fields
2013-05-20 15:02:08 +00:00
SIInstrInfo.cpp
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SIInstrInfo.h
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SIInstrInfo.td
Cast to the correct type. Pointer, not reference.
2013-06-06 05:39:29 +00:00
SIInstructions.td
R600/SI: Add support for global loads
2013-06-03 17:39:43 +00:00
SIIntrinsics.td
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SIISelLowering.cpp
R600: Replace predicate loop with predicate function
2013-06-05 23:39:50 +00:00
SIISelLowering.h
R600/SI: Add support for work item and work group intrinsics
2013-06-03 17:40:18 +00:00
SILowerControlFlow.cpp
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SIMachineFunctionInfo.cpp
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SIMachineFunctionInfo.h
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SIRegisterInfo.cpp
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SIRegisterInfo.h
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SIRegisterInfo.td
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SISchedule.td
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