llvm-6502

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History

Evan Cheng 15213b77cf SIGN_EXTEND_INREG requires one extra operand, a ValueType node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35350 91177308-0d34-0410-b5e6-96231b3b80d8		2007-03-26 07:12:51 +00:00
..
SelectionDAG	SIGN_EXTEND_INREG requires one extra operand, a ValueType node.	2007-03-26 07:12:51 +00:00
AsmPrinter.cpp
BranchFolding.cpp
DwarfWriter.cpp
ELFWriter.cpp
ELFWriter.h
IntrinsicLowering.cpp
LiveInterval.cpp
LiveIntervalAnalysis.cpp
LiveVariables.cpp
LLVMTargetMachine.cpp
MachineBasicBlock.cpp
MachineFunction.cpp
MachineInstr.cpp
MachineModuleInfo.cpp
MachinePassRegistry.cpp
MachOWriter.cpp
MachOWriter.h
Makefile
Passes.cpp
PHIElimination.cpp
PhysRegTracker.h
PrologEpilogInserter.cpp
README.txt
RegAllocLinearScan.cpp
RegAllocLocal.cpp
RegAllocSimple.cpp
RegisterScavenging.cpp
TwoAddressInstructionPass.cpp
UnreachableBlockElim.cpp
VirtRegMap.cpp
VirtRegMap.h

README.txt

Common register allocation / spilling problem:

	mul lr, r4, lr
	str lr, [sp, #+52]
	ldr lr, [r1, #+32]
	sxth r3, r3
	ldr r4, [sp, #+52]
	mla r4, r3, lr, r4

can be:

	mul lr, r4, lr
        mov r4, lr
	str lr, [sp, #+52]
	ldr lr, [r1, #+32]
	sxth r3, r3
	mla r4, r3, lr, r4

and then "merge" mul and mov:

	mul r4, r4, lr
	str lr, [sp, #+52]
	ldr lr, [r1, #+32]
	sxth r3, r3
	mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.