mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-16 00:33:10 +00:00
f317d86f8f
Move / delete some of the more obviously wrong setOperationAction calls. Most of these are setting Expand for types that aren't legal which is the default anyway. Leave stuff that might require more thought on whether it's junk or not as it is. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210922 91177308-0d34-0410-b5e6-96231b3b80d8
473 lines
13 KiB
C++
473 lines
13 KiB
C++
//===-- AMDILISelLowering.cpp - AMDIL DAG Lowering Implementation ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//==-----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief TargetLowering functions borrowed from AMDIL.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUISelLowering.h"
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#include "AMDGPURegisterInfo.h"
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#include "AMDGPUSubtarget.h"
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#include "AMDILIntrinsicInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// TargetLowering Implementation Help Functions End
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// TargetLowering Class Implementation Begins
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//===----------------------------------------------------------------------===//
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void AMDGPUTargetLowering::InitAMDILLowering() {
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static const MVT::SimpleValueType types[] = {
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MVT::i32,
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MVT::f32,
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MVT::f64,
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MVT::i64,
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MVT::v4f32,
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MVT::v4i32,
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MVT::v2f32,
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MVT::v2i32
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};
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static const MVT::SimpleValueType FloatTypes[] = {
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MVT::f32,
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MVT::f64
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};
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static const MVT::SimpleValueType VectorTypes[] = {
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MVT::v4f32,
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MVT::v4i32,
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MVT::v2f32,
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MVT::v2i32
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};
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const AMDGPUSubtarget &STM = getTargetMachine().getSubtarget<AMDGPUSubtarget>();
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for (MVT VT : types) {
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setOperationAction(ISD::SUBE, VT, Expand);
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setOperationAction(ISD::SUBC, VT, Expand);
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setOperationAction(ISD::ADDE, VT, Expand);
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setOperationAction(ISD::ADDC, VT, Expand);
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setOperationAction(ISD::BRCOND, VT, Custom);
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setOperationAction(ISD::BR_JT, VT, Expand);
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setOperationAction(ISD::BRIND, VT, Expand);
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// TODO: Implement custom UREM/SREM routines
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setOperationAction(ISD::SREM, VT, Expand);
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setOperationAction(ISD::SMUL_LOHI, VT, Expand);
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setOperationAction(ISD::UMUL_LOHI, VT, Expand);
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if (VT != MVT::i64)
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setOperationAction(ISD::SDIV, VT, Custom);
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}
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for (MVT VT : FloatTypes) {
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setOperationAction(ISD::FP_ROUND_INREG, VT, Expand);
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}
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for (MVT VT : VectorTypes) {
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setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
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setOperationAction(ISD::SELECT_CC, VT, Expand);
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}
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setOperationAction(ISD::MULHU, MVT::i64, Expand);
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setOperationAction(ISD::MULHS, MVT::i64, Expand);
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if (STM.hasHWFP64()) {
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setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
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setOperationAction(ISD::FABS, MVT::f64, Expand);
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}
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setOperationAction(ISD::SUBC, MVT::Other, Expand);
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setOperationAction(ISD::ADDE, MVT::Other, Expand);
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setOperationAction(ISD::ADDC, MVT::Other, Expand);
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setOperationAction(ISD::BRCOND, MVT::Other, Custom);
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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setOperationAction(ISD::BRIND, MVT::Other, Expand);
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setOperationAction(ISD::Constant, MVT::i32, Legal);
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setOperationAction(ISD::Constant, MVT::i64, Legal);
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setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
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setPow2DivIsCheap(false);
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setSelectIsExpensive(true); // FIXME: This makes no sense at all
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}
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bool
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AMDGPUTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
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const CallInst &I, unsigned Intrinsic) const {
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return false;
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}
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// The backend supports 32 and 64 bit floating point immediates
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bool
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AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
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if (VT.getScalarType().getSimpleVT().SimpleTy == MVT::f32
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|| VT.getScalarType().getSimpleVT().SimpleTy == MVT::f64) {
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return true;
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} else {
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return false;
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}
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}
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bool
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AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
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if (VT.getScalarType().getSimpleVT().SimpleTy == MVT::f32
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|| VT.getScalarType().getSimpleVT().SimpleTy == MVT::f64) {
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return false;
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} else {
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return true;
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}
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}
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// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
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// be zero. Op is expected to be a target specific node. Used by DAG
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// combiner.
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//===----------------------------------------------------------------------===//
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// Other Lowering Hooks
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//===----------------------------------------------------------------------===//
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SDValue
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AMDGPUTargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const {
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EVT OVT = Op.getValueType();
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SDValue DST;
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if (OVT.getScalarType() == MVT::i64) {
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DST = LowerSDIV64(Op, DAG);
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} else if (OVT.getScalarType() == MVT::i32) {
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DST = LowerSDIV32(Op, DAG);
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} else if (OVT.getScalarType() == MVT::i16
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|| OVT.getScalarType() == MVT::i8) {
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DST = LowerSDIV24(Op, DAG);
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} else {
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DST = SDValue(Op.getNode(), 0);
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}
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return DST;
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}
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SDValue
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AMDGPUTargetLowering::LowerSREM(SDValue Op, SelectionDAG &DAG) const {
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EVT OVT = Op.getValueType();
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SDValue DST;
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if (OVT.getScalarType() == MVT::i64) {
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DST = LowerSREM64(Op, DAG);
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} else if (OVT.getScalarType() == MVT::i32) {
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DST = LowerSREM32(Op, DAG);
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} else if (OVT.getScalarType() == MVT::i16) {
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DST = LowerSREM16(Op, DAG);
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} else if (OVT.getScalarType() == MVT::i8) {
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DST = LowerSREM8(Op, DAG);
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} else {
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DST = SDValue(Op.getNode(), 0);
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}
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return DST;
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}
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EVT
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AMDGPUTargetLowering::genIntType(uint32_t size, uint32_t numEle) const {
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int iSize = (size * numEle);
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int vEle = (iSize >> ((size == 64) ? 6 : 5));
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if (!vEle) {
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vEle = 1;
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}
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if (size == 64) {
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if (vEle == 1) {
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return EVT(MVT::i64);
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} else {
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return EVT(MVT::getVectorVT(MVT::i64, vEle));
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}
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} else {
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if (vEle == 1) {
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return EVT(MVT::i32);
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} else {
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return EVT(MVT::getVectorVT(MVT::i32, vEle));
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}
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}
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}
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SDValue
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AMDGPUTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
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SDValue Chain = Op.getOperand(0);
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SDValue Cond = Op.getOperand(1);
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SDValue Jump = Op.getOperand(2);
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SDValue Result;
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Result = DAG.getNode(
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AMDGPUISD::BRANCH_COND,
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SDLoc(Op),
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Op.getValueType(),
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Chain, Jump, Cond);
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return Result;
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}
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SDValue
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AMDGPUTargetLowering::LowerSDIV24(SDValue Op, SelectionDAG &DAG) const {
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SDLoc DL(Op);
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EVT OVT = Op.getValueType();
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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MVT INTTY;
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MVT FLTTY;
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if (!OVT.isVector()) {
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INTTY = MVT::i32;
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FLTTY = MVT::f32;
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} else if (OVT.getVectorNumElements() == 2) {
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INTTY = MVT::v2i32;
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FLTTY = MVT::v2f32;
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} else if (OVT.getVectorNumElements() == 4) {
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INTTY = MVT::v4i32;
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FLTTY = MVT::v4f32;
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}
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unsigned bitsize = OVT.getScalarType().getSizeInBits();
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// char|short jq = ia ^ ib;
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SDValue jq = DAG.getNode(ISD::XOR, DL, OVT, LHS, RHS);
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// jq = jq >> (bitsize - 2)
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jq = DAG.getNode(ISD::SRA, DL, OVT, jq, DAG.getConstant(bitsize - 2, OVT));
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// jq = jq | 0x1
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jq = DAG.getNode(ISD::OR, DL, OVT, jq, DAG.getConstant(1, OVT));
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// jq = (int)jq
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jq = DAG.getSExtOrTrunc(jq, DL, INTTY);
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// int ia = (int)LHS;
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SDValue ia = DAG.getSExtOrTrunc(LHS, DL, INTTY);
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// int ib, (int)RHS;
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SDValue ib = DAG.getSExtOrTrunc(RHS, DL, INTTY);
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// float fa = (float)ia;
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SDValue fa = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ia);
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// float fb = (float)ib;
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SDValue fb = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ib);
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// float fq = native_divide(fa, fb);
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SDValue fq = DAG.getNode(AMDGPUISD::DIV_INF, DL, FLTTY, fa, fb);
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// fq = trunc(fq);
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fq = DAG.getNode(ISD::FTRUNC, DL, FLTTY, fq);
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// float fqneg = -fq;
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SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FLTTY, fq);
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// float fr = mad(fqneg, fb, fa);
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SDValue fr = DAG.getNode(ISD::FADD, DL, FLTTY,
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DAG.getNode(ISD::MUL, DL, FLTTY, fqneg, fb), fa);
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// int iq = (int)fq;
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SDValue iq = DAG.getNode(ISD::FP_TO_SINT, DL, INTTY, fq);
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// fr = fabs(fr);
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fr = DAG.getNode(ISD::FABS, DL, FLTTY, fr);
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// fb = fabs(fb);
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fb = DAG.getNode(ISD::FABS, DL, FLTTY, fb);
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// int cv = fr >= fb;
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SDValue cv;
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if (INTTY == MVT::i32) {
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cv = DAG.getSetCC(DL, INTTY, fr, fb, ISD::SETOGE);
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} else {
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cv = DAG.getSetCC(DL, INTTY, fr, fb, ISD::SETOGE);
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}
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// jq = (cv ? jq : 0);
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jq = DAG.getNode(ISD::SELECT, DL, OVT, cv, jq,
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DAG.getConstant(0, OVT));
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// dst = iq + jq;
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iq = DAG.getSExtOrTrunc(iq, DL, OVT);
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iq = DAG.getNode(ISD::ADD, DL, OVT, iq, jq);
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return iq;
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}
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SDValue
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AMDGPUTargetLowering::LowerSDIV32(SDValue Op, SelectionDAG &DAG) const {
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SDLoc DL(Op);
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EVT OVT = Op.getValueType();
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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// The LowerSDIV32 function generates equivalent to the following IL.
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// mov r0, LHS
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// mov r1, RHS
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// ilt r10, r0, 0
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// ilt r11, r1, 0
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// iadd r0, r0, r10
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// iadd r1, r1, r11
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// ixor r0, r0, r10
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// ixor r1, r1, r11
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// udiv r0, r0, r1
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// ixor r10, r10, r11
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// iadd r0, r0, r10
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// ixor DST, r0, r10
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// mov r0, LHS
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SDValue r0 = LHS;
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// mov r1, RHS
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SDValue r1 = RHS;
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// ilt r10, r0, 0
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SDValue r10 = DAG.getSelectCC(DL,
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r0, DAG.getConstant(0, OVT),
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DAG.getConstant(-1, MVT::i32),
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DAG.getConstant(0, MVT::i32),
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ISD::SETLT);
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// ilt r11, r1, 0
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SDValue r11 = DAG.getSelectCC(DL,
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r1, DAG.getConstant(0, OVT),
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DAG.getConstant(-1, MVT::i32),
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DAG.getConstant(0, MVT::i32),
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ISD::SETLT);
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// iadd r0, r0, r10
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r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
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// iadd r1, r1, r11
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r1 = DAG.getNode(ISD::ADD, DL, OVT, r1, r11);
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// ixor r0, r0, r10
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r0 = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
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// ixor r1, r1, r11
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r1 = DAG.getNode(ISD::XOR, DL, OVT, r1, r11);
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// udiv r0, r0, r1
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r0 = DAG.getNode(ISD::UDIV, DL, OVT, r0, r1);
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// ixor r10, r10, r11
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r10 = DAG.getNode(ISD::XOR, DL, OVT, r10, r11);
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// iadd r0, r0, r10
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r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
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// ixor DST, r0, r10
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SDValue DST = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
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return DST;
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}
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SDValue
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AMDGPUTargetLowering::LowerSDIV64(SDValue Op, SelectionDAG &DAG) const {
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return SDValue(Op.getNode(), 0);
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}
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SDValue
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AMDGPUTargetLowering::LowerSREM8(SDValue Op, SelectionDAG &DAG) const {
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SDLoc DL(Op);
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EVT OVT = Op.getValueType();
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MVT INTTY = MVT::i32;
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if (OVT == MVT::v2i8) {
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INTTY = MVT::v2i32;
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} else if (OVT == MVT::v4i8) {
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INTTY = MVT::v4i32;
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}
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SDValue LHS = DAG.getSExtOrTrunc(Op.getOperand(0), DL, INTTY);
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SDValue RHS = DAG.getSExtOrTrunc(Op.getOperand(1), DL, INTTY);
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LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS);
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LHS = DAG.getSExtOrTrunc(LHS, DL, OVT);
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return LHS;
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}
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SDValue
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AMDGPUTargetLowering::LowerSREM16(SDValue Op, SelectionDAG &DAG) const {
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SDLoc DL(Op);
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EVT OVT = Op.getValueType();
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MVT INTTY = MVT::i32;
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if (OVT == MVT::v2i16) {
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INTTY = MVT::v2i32;
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} else if (OVT == MVT::v4i16) {
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INTTY = MVT::v4i32;
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}
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SDValue LHS = DAG.getSExtOrTrunc(Op.getOperand(0), DL, INTTY);
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SDValue RHS = DAG.getSExtOrTrunc(Op.getOperand(1), DL, INTTY);
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LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS);
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LHS = DAG.getSExtOrTrunc(LHS, DL, OVT);
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return LHS;
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}
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SDValue
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AMDGPUTargetLowering::LowerSREM32(SDValue Op, SelectionDAG &DAG) const {
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SDLoc DL(Op);
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EVT OVT = Op.getValueType();
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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// The LowerSREM32 function generates equivalent to the following IL.
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// mov r0, LHS
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// mov r1, RHS
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// ilt r10, r0, 0
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// ilt r11, r1, 0
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// iadd r0, r0, r10
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// iadd r1, r1, r11
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// ixor r0, r0, r10
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// ixor r1, r1, r11
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// udiv r20, r0, r1
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// umul r20, r20, r1
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// sub r0, r0, r20
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// iadd r0, r0, r10
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// ixor DST, r0, r10
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// mov r0, LHS
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SDValue r0 = LHS;
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// mov r1, RHS
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SDValue r1 = RHS;
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// ilt r10, r0, 0
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SDValue r10 = DAG.getSetCC(DL, OVT, r0, DAG.getConstant(0, OVT), ISD::SETLT);
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// ilt r11, r1, 0
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SDValue r11 = DAG.getSetCC(DL, OVT, r1, DAG.getConstant(0, OVT), ISD::SETLT);
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// iadd r0, r0, r10
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r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
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// iadd r1, r1, r11
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r1 = DAG.getNode(ISD::ADD, DL, OVT, r1, r11);
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// ixor r0, r0, r10
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r0 = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
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// ixor r1, r1, r11
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r1 = DAG.getNode(ISD::XOR, DL, OVT, r1, r11);
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// udiv r20, r0, r1
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SDValue r20 = DAG.getNode(ISD::UREM, DL, OVT, r0, r1);
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// umul r20, r20, r1
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r20 = DAG.getNode(AMDGPUISD::UMUL, DL, OVT, r20, r1);
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// sub r0, r0, r20
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r0 = DAG.getNode(ISD::SUB, DL, OVT, r0, r20);
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// iadd r0, r0, r10
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r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
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// ixor DST, r0, r10
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SDValue DST = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
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return DST;
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}
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SDValue
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AMDGPUTargetLowering::LowerSREM64(SDValue Op, SelectionDAG &DAG) const {
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return SDValue(Op.getNode(), 0);
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}
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