LLVM backend for 6502
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Jakob Stoklund Olesen f0a804df49 Allow direct value types in pattern definitions.
Just like register classes, value types can be used in two ways in
patterns:

  (sext_inreg i32:$src, i16)

In a named leaf node like i32:$src, the value type simply provides the
type of the node directly. This simplifies type inference a lot compared
to the current practice of specifiying types indirectly with register
classes.

As an unnamed leaf node, like i16 above, the value type represents
itself as an MVT::Other immediate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177828 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23 20:35:01 +00:00
autoconf
bindings
cmake Enable -Wnon-virtual-dtor build warning 2013-03-19 10:10:03 +00:00
docs [docs] Slight reword for precision. 2013-03-22 23:52:38 +00:00
examples
include Allow the register scavenger to spill multiple registers 2013-03-22 23:32:27 +00:00
lib Cleanup some unused reg. scavenger parameters in PPCRegisterInfo 2013-03-23 19:36:47 +00:00
projects
runtime
test Move X86-dependent test into the right subdirectory. 2013-03-23 09:35:44 +00:00
tools Remove stale comment 2013-03-19 16:04:02 +00:00
unittests
utils Allow direct value types in pattern definitions. 2013-03-23 20:35:01 +00:00
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LICENSE.TXT
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Low Level Virtual Machine (LLVM)
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