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https://github.com/c64scene-ar/llvm-6502.git
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7e413e9c94
In this patch we optimize this pattern and convert the sequence into extract op of a narrow type. This allows the BUILD_VECTOR dag optimizations to construct efficient shuffle operations in many cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149692 91177308-0d34-0410-b5e6-96231b3b80d8
120 lines
4.2 KiB
LLVM
120 lines
4.2 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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; PR11102
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define <4 x float> @test1(<4 x float> %a) nounwind {
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%b = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 2, i32 5, i32 undef, i32 undef>
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ret <4 x float> %b
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; CHECK: test1:
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; CHECK: vshufps
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; CHECK: vpshufd
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}
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; rdar://10538417
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define <3 x i64> @test2(<2 x i64> %v) nounwind readnone {
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; CHECK: test2:
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; CHECK: vinsertf128
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%1 = shufflevector <2 x i64> %v, <2 x i64> %v, <3 x i32> <i32 0, i32 1, i32 undef>
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%2 = shufflevector <3 x i64> zeroinitializer, <3 x i64> %1, <3 x i32> <i32 3, i32 4, i32 2>
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ret <3 x i64> %2
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; CHECK: ret
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}
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define <4 x i64> @test3(<4 x i64> %a, <4 x i64> %b) nounwind {
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%c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 4, i32 5, i32 2, i32 undef>
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ret <4 x i64> %c
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; CHECK: test3:
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; CHECK: vperm2f128
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; CHECK: ret
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}
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define <8 x float> @test4(float %a) nounwind {
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%b = insertelement <8 x float> zeroinitializer, float %a, i32 0
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ret <8 x float> %b
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; CHECK: test4:
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; CHECK: vinsertf128
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}
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; rdar://10594409
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define <8 x float> @test5(float* nocapture %f) nounwind uwtable readonly ssp {
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entry:
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%0 = bitcast float* %f to <4 x float>*
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%1 = load <4 x float>* %0, align 16
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; CHECK: test5
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; CHECK: vmovaps
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; CHECK-NOT: vxorps
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; CHECK-NOT: vinsertf128
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%shuffle.i = shufflevector <4 x float> %1, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 4, i32 4>
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ret <8 x float> %shuffle.i
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}
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define <4 x double> @test6(double* nocapture %d) nounwind uwtable readonly ssp {
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entry:
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%0 = bitcast double* %d to <2 x double>*
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%1 = load <2 x double>* %0, align 16
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; CHECK: test6
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; CHECK: vmovaps
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; CHECK-NOT: vxorps
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; CHECK-NOT: vinsertf128
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%shuffle.i = shufflevector <2 x double> %1, <2 x double> <double 0.000000e+00, double undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
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ret <4 x double> %shuffle.i
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}
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define <16 x i16> @test7(<4 x i16> %a) nounwind {
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; CHECK: test7
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%b = shufflevector <4 x i16> %a, <4 x i16> undef, <16 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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; CHECK: ret
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ret <16 x i16> %b
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}
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; CHECK: test8
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define void @test8() {
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entry:
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%0 = load <16 x i64> addrspace(1)* null, align 128
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%1 = shufflevector <16 x i64> <i64 undef, i64 undef, i64 0, i64 undef, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 undef, i64 0, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i64> %0, <16 x i32> <i32 17, i32 18, i32 2, i32 undef, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 undef, i32 11, i32 undef, i32 undef, i32 undef, i32 26>
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%2 = shufflevector <16 x i64> %1, <16 x i64> %0, <16 x i32> <i32 0, i32 1, i32 2, i32 30, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 undef, i32 11, i32 undef, i32 22, i32 20, i32 15>
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store <16 x i64> %2, <16 x i64> addrspace(1)* undef, align 128
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; CHECK: ret
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ret void
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}
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; Extract a value from a shufflevector..
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define i32 @test9(<4 x i32> %a) nounwind {
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; CHECK: test9
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; CHECK: vpextrd
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%b = shufflevector <4 x i32> %a, <4 x i32> undef, <8 x i32> <i32 1, i32 1, i32 2, i32 2, i32 3, i32 3, i32 undef, i32 4>
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%r = extractelement <8 x i32> %b, i32 2
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; CHECK: ret
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ret i32 %r
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}
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; Extract a value which is the result of an undef mask.
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define i32 @test10(<4 x i32> %a) nounwind {
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; CHECK: @test10
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; CHECK-NEXT: #
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; CHECK-NEXT: ret
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%b = shufflevector <4 x i32> %a, <4 x i32> undef, <8 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%r = extractelement <8 x i32> %b, i32 2
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ret i32 %r
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}
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define <4 x float> @test11(<4 x float> %a) nounwind {
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; CHECK: pshufd $27
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%tmp1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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ret <4 x float> %tmp1
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}
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define <4 x float> @test12(<4 x float>* %a) nounwind {
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; CHECK: pshufd $27, (
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%tmp0 = load <4 x float>* %a
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%tmp1 = shufflevector <4 x float> %tmp0, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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ret <4 x float> %tmp1
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}
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;CHECK: test13
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;CHECK: shufd
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;CHECK: ret
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define <4 x i32> @test13(<2 x i32>%x) nounwind readnone {
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%x1 = shufflevector <2 x i32> %x, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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ret <4 x i32>%x1
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}
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