mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-10-31 08:16:47 +00:00
6c7ccaa3fd
- BlockAddress has no support of BA + offset form and there is no way to propagate that offset into machine operand; - Add BA + offset support and a new interface 'getTargetBlockAddress' to simplify target block address forming; - All targets are modified to use new interface and X86 backend is enhanced to support BA + offset addressing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163743 91177308-0d34-0410-b5e6-96231b3b80d8
990 lines
40 KiB
C++
990 lines
40 KiB
C++
//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements the Emit routines for the SelectionDAG class, which creates
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// MachineInstrs based on the decisions of the SelectionDAG instruction
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// selection.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "instr-emitter"
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#include "InstrEmitter.h"
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#include "SDNodeDbgValue.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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using namespace llvm;
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/// MinRCSize - Smallest register class we allow when constraining virtual
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/// registers. If satisfying all register class constraints would require
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/// using a smaller register class, emit a COPY to a new virtual register
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/// instead.
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const unsigned MinRCSize = 4;
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/// CountResults - The results of target nodes have register or immediate
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/// operands first, then an optional chain, and optional glue operands (which do
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/// not go into the resulting MachineInstr).
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unsigned InstrEmitter::CountResults(SDNode *Node) {
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unsigned N = Node->getNumValues();
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while (N && Node->getValueType(N - 1) == MVT::Glue)
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--N;
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if (N && Node->getValueType(N - 1) == MVT::Other)
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--N; // Skip over chain result.
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return N;
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}
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/// countOperands - The inputs to target nodes have any actual inputs first,
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/// followed by an optional chain operand, then an optional glue operand.
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/// Compute the number of actual operands that will go into the resulting
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/// MachineInstr.
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///
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/// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
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/// the chain and glue. These operands may be implicit on the machine instr.
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static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
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unsigned &NumImpUses) {
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unsigned N = Node->getNumOperands();
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while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
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--N;
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if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
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--N; // Ignore chain if it exists.
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// Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
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NumImpUses = N - NumExpUses;
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for (unsigned I = N; I > NumExpUses; --I) {
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if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
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continue;
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if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
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if (TargetRegisterInfo::isPhysicalRegister(RN->getReg()))
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continue;
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NumImpUses = N - I;
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break;
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}
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return N;
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}
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/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
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/// implicit physical register output.
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void InstrEmitter::
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EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
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unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
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unsigned VRBase = 0;
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if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
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// Just use the input register directly!
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SDValue Op(Node, ResNo);
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if (IsClone)
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VRBaseMap.erase(Op);
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bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
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(void)isNew; // Silence compiler warning.
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assert(isNew && "Node emitted out of order - early");
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return;
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}
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// If the node is only used by a CopyToReg and the dest reg is a vreg, use
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// the CopyToReg'd destination register instead of creating a new vreg.
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bool MatchReg = true;
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const TargetRegisterClass *UseRC = NULL;
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EVT VT = Node->getValueType(ResNo);
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// Stick to the preferred register classes for legal types.
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if (TLI->isTypeLegal(VT))
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UseRC = TLI->getRegClassFor(VT);
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if (!IsClone && !IsCloned)
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for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
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UI != E; ++UI) {
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SDNode *User = *UI;
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bool Match = true;
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if (User->getOpcode() == ISD::CopyToReg &&
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User->getOperand(2).getNode() == Node &&
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User->getOperand(2).getResNo() == ResNo) {
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unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
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if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
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VRBase = DestReg;
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Match = false;
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} else if (DestReg != SrcReg)
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Match = false;
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} else {
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for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
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SDValue Op = User->getOperand(i);
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if (Op.getNode() != Node || Op.getResNo() != ResNo)
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continue;
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EVT VT = Node->getValueType(Op.getResNo());
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if (VT == MVT::Other || VT == MVT::Glue)
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continue;
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Match = false;
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if (User->isMachineOpcode()) {
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const MCInstrDesc &II = TII->get(User->getMachineOpcode());
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const TargetRegisterClass *RC = 0;
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if (i+II.getNumDefs() < II.getNumOperands()) {
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RC = TRI->getAllocatableClass(
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TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
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}
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if (!UseRC)
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UseRC = RC;
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else if (RC) {
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const TargetRegisterClass *ComRC =
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TRI->getCommonSubClass(UseRC, RC);
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// If multiple uses expect disjoint register classes, we emit
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// copies in AddRegisterOperand.
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if (ComRC)
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UseRC = ComRC;
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}
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}
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}
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}
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MatchReg &= Match;
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if (VRBase)
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break;
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}
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const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
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SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
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// Figure out the register class to create for the destreg.
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if (VRBase) {
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DstRC = MRI->getRegClass(VRBase);
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} else if (UseRC) {
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assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
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DstRC = UseRC;
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} else {
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DstRC = TLI->getRegClassFor(VT);
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}
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// If all uses are reading from the src physical register and copying the
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// register is either impossible or very expensive, then don't create a copy.
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if (MatchReg && SrcRC->getCopyCost() < 0) {
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VRBase = SrcReg;
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} else {
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// Create the reg, emit the copy.
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VRBase = MRI->createVirtualRegister(DstRC);
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BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
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VRBase).addReg(SrcReg);
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}
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SDValue Op(Node, ResNo);
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if (IsClone)
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VRBaseMap.erase(Op);
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bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
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(void)isNew; // Silence compiler warning.
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assert(isNew && "Node emitted out of order - early");
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}
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/// getDstOfCopyToRegUse - If the only use of the specified result number of
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/// node is a CopyToReg, return its destination register. Return 0 otherwise.
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unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node,
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unsigned ResNo) const {
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if (!Node->hasOneUse())
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return 0;
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SDNode *User = *Node->use_begin();
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if (User->getOpcode() == ISD::CopyToReg &&
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User->getOperand(2).getNode() == Node &&
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User->getOperand(2).getResNo() == ResNo) {
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unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg))
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return Reg;
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}
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return 0;
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}
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void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
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const MCInstrDesc &II,
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bool IsClone, bool IsCloned,
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DenseMap<SDValue, unsigned> &VRBaseMap) {
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assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
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"IMPLICIT_DEF should have been handled as a special case elsewhere!");
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for (unsigned i = 0; i < II.getNumDefs(); ++i) {
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// If the specific node value is only used by a CopyToReg and the dest reg
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// is a vreg in the same register class, use the CopyToReg'd destination
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// register instead of creating a new vreg.
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unsigned VRBase = 0;
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const TargetRegisterClass *RC =
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TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
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if (II.OpInfo[i].isOptionalDef()) {
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// Optional def must be a physical register.
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unsigned NumResults = CountResults(Node);
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VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
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assert(TargetRegisterInfo::isPhysicalRegister(VRBase));
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MI->addOperand(MachineOperand::CreateReg(VRBase, true));
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}
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if (!VRBase && !IsClone && !IsCloned)
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for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
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UI != E; ++UI) {
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SDNode *User = *UI;
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if (User->getOpcode() == ISD::CopyToReg &&
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User->getOperand(2).getNode() == Node &&
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User->getOperand(2).getResNo() == i) {
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unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
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if (RegRC == RC) {
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VRBase = Reg;
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MI->addOperand(MachineOperand::CreateReg(Reg, true));
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break;
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}
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}
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}
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}
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// Create the result registers for this node and add the result regs to
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// the machine instruction.
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if (VRBase == 0) {
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assert(RC && "Isn't a register operand!");
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VRBase = MRI->createVirtualRegister(RC);
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MI->addOperand(MachineOperand::CreateReg(VRBase, true));
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}
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SDValue Op(Node, i);
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if (IsClone)
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VRBaseMap.erase(Op);
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bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
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(void)isNew; // Silence compiler warning.
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assert(isNew && "Node emitted out of order - early");
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}
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}
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/// getVR - Return the virtual register corresponding to the specified result
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/// of the specified node.
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unsigned InstrEmitter::getVR(SDValue Op,
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DenseMap<SDValue, unsigned> &VRBaseMap) {
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if (Op.isMachineOpcode() &&
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Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
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// Add an IMPLICIT_DEF instruction before every use.
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unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
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// IMPLICIT_DEF can produce any type of result so its MCInstrDesc
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// does not include operand register class info.
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if (!VReg) {
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const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType());
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VReg = MRI->createVirtualRegister(RC);
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}
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BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
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TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
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return VReg;
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}
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DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
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assert(I != VRBaseMap.end() && "Node emitted out of order - late");
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return I->second;
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}
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/// AddRegisterOperand - Add the specified register as an operand to the
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/// specified machine instr. Insert register copies if the register is
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/// not in the required register class.
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void
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InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
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unsigned IIOpNum,
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const MCInstrDesc *II,
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DenseMap<SDValue, unsigned> &VRBaseMap,
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bool IsDebug, bool IsClone, bool IsCloned) {
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assert(Op.getValueType() != MVT::Other &&
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Op.getValueType() != MVT::Glue &&
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"Chain and glue operands should occur at end of operand list!");
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// Get/emit the operand.
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unsigned VReg = getVR(Op, VRBaseMap);
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assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
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const MCInstrDesc &MCID = MI->getDesc();
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bool isOptDef = IIOpNum < MCID.getNumOperands() &&
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MCID.OpInfo[IIOpNum].isOptionalDef();
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// If the instruction requires a register in a different class, create
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// a new virtual register and copy the value into it, but first attempt to
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// shrink VReg's register class within reason. For example, if VReg == GR32
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// and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
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if (II) {
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const TargetRegisterClass *DstRC = 0;
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if (IIOpNum < II->getNumOperands())
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DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
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if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
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unsigned NewVReg = MRI->createVirtualRegister(DstRC);
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BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
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TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
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VReg = NewVReg;
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}
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}
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// If this value has only one use, that use is a kill. This is a
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// conservative approximation. InstrEmitter does trivial coalescing
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// with CopyFromReg nodes, so don't emit kill flags for them.
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// Avoid kill flags on Schedule cloned nodes, since there will be
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// multiple uses.
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// Tied operands are never killed, so we need to check that. And that
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// means we need to determine the index of the operand.
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bool isKill = Op.hasOneUse() &&
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Op.getNode()->getOpcode() != ISD::CopyFromReg &&
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!IsDebug &&
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!(IsClone || IsCloned);
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if (isKill) {
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unsigned Idx = MI->getNumOperands();
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while (Idx > 0 &&
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MI->getOperand(Idx-1).isReg() && MI->getOperand(Idx-1).isImplicit())
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--Idx;
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bool isTied = MI->getDesc().getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
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if (isTied)
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isKill = false;
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}
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MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef,
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false/*isImp*/, isKill,
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false/*isDead*/, false/*isUndef*/,
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false/*isEarlyClobber*/,
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0/*SubReg*/, IsDebug));
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}
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/// AddOperand - Add the specified operand to the specified machine instr. II
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/// specifies the instruction information for the node, and IIOpNum is the
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/// operand number (in the II) that we are adding.
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void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op,
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unsigned IIOpNum,
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const MCInstrDesc *II,
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DenseMap<SDValue, unsigned> &VRBaseMap,
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bool IsDebug, bool IsClone, bool IsCloned) {
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if (Op.isMachineOpcode()) {
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AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap,
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IsDebug, IsClone, IsCloned);
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} else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
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MI->addOperand(MachineOperand::CreateImm(C->getSExtValue()));
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} else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
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const ConstantFP *CFP = F->getConstantFPValue();
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MI->addOperand(MachineOperand::CreateFPImm(CFP));
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} else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
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// Turn additional physreg operands into implicit uses on non-variadic
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// instructions. This is used by call and return instructions passing
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// arguments in registers.
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bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
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MI->addOperand(MachineOperand::CreateReg(R->getReg(), false, Imp));
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} else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
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MI->addOperand(MachineOperand::CreateRegMask(RM->getRegMask()));
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} else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
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MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(),
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TGA->getTargetFlags()));
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} else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
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MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock()));
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} else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
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MI->addOperand(MachineOperand::CreateFI(FI->getIndex()));
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} else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
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MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(),
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JT->getTargetFlags()));
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} else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
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int Offset = CP->getOffset();
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unsigned Align = CP->getAlignment();
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Type *Type = CP->getType();
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// MachineConstantPool wants an explicit alignment.
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if (Align == 0) {
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Align = TM->getTargetData()->getPrefTypeAlignment(Type);
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if (Align == 0) {
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// Alignment of vector types. FIXME!
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Align = TM->getTargetData()->getTypeAllocSize(Type);
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}
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}
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unsigned Idx;
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MachineConstantPool *MCP = MF->getConstantPool();
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if (CP->isMachineConstantPoolEntry())
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Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
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else
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Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
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MI->addOperand(MachineOperand::CreateCPI(Idx, Offset,
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CP->getTargetFlags()));
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} else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
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MI->addOperand(MachineOperand::CreateES(ES->getSymbol(),
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ES->getTargetFlags()));
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} else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
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MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress(),
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BA->getOffset(),
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BA->getTargetFlags()));
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} else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
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MI->addOperand(MachineOperand::CreateTargetIndex(TI->getIndex(),
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TI->getOffset(),
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TI->getTargetFlags()));
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} else {
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assert(Op.getValueType() != MVT::Other &&
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Op.getValueType() != MVT::Glue &&
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"Chain and glue operands should occur at end of operand list!");
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AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap,
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IsDebug, IsClone, IsCloned);
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}
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}
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unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
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EVT VT, DebugLoc DL) {
|
|
const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
|
|
const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
|
|
|
|
// RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
|
|
// within reason.
|
|
if (RC && RC != VRC)
|
|
RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
|
|
|
|
// VReg has been adjusted. It can be used with SubIdx operands now.
|
|
if (RC)
|
|
return VReg;
|
|
|
|
// VReg couldn't be reasonably constrained. Emit a COPY to a new virtual
|
|
// register instead.
|
|
RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx);
|
|
assert(RC && "No legal register class for VT supports that SubIdx");
|
|
unsigned NewReg = MRI->createVirtualRegister(RC);
|
|
BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
|
|
.addReg(VReg);
|
|
return NewReg;
|
|
}
|
|
|
|
/// EmitSubregNode - Generate machine code for subreg nodes.
|
|
///
|
|
void InstrEmitter::EmitSubregNode(SDNode *Node,
|
|
DenseMap<SDValue, unsigned> &VRBaseMap,
|
|
bool IsClone, bool IsCloned) {
|
|
unsigned VRBase = 0;
|
|
unsigned Opc = Node->getMachineOpcode();
|
|
|
|
// If the node is only used by a CopyToReg and the dest reg is a vreg, use
|
|
// the CopyToReg'd destination register instead of creating a new vreg.
|
|
for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
|
|
UI != E; ++UI) {
|
|
SDNode *User = *UI;
|
|
if (User->getOpcode() == ISD::CopyToReg &&
|
|
User->getOperand(2).getNode() == Node) {
|
|
unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
|
|
if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
|
|
VRBase = DestReg;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (Opc == TargetOpcode::EXTRACT_SUBREG) {
|
|
// EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no
|
|
// constraints on the %dst register, COPY can target all legal register
|
|
// classes.
|
|
unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
|
|
const TargetRegisterClass *TRC = TLI->getRegClassFor(Node->getValueType(0));
|
|
|
|
unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
|
|
MachineInstr *DefMI = MRI->getVRegDef(VReg);
|
|
unsigned SrcReg, DstReg, DefSubIdx;
|
|
if (DefMI &&
|
|
TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
|
|
SubIdx == DefSubIdx &&
|
|
TRC == MRI->getRegClass(SrcReg)) {
|
|
// Optimize these:
|
|
// r1025 = s/zext r1024, 4
|
|
// r1026 = extract_subreg r1025, 4
|
|
// to a copy
|
|
// r1026 = copy r1024
|
|
VRBase = MRI->createVirtualRegister(TRC);
|
|
BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
|
|
TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
|
|
MRI->clearKillFlags(SrcReg);
|
|
} else {
|
|
// VReg may not support a SubIdx sub-register, and we may need to
|
|
// constrain its register class or issue a COPY to a compatible register
|
|
// class.
|
|
VReg = ConstrainForSubReg(VReg, SubIdx,
|
|
Node->getOperand(0).getValueType(),
|
|
Node->getDebugLoc());
|
|
|
|
// Create the destreg if it is missing.
|
|
if (VRBase == 0)
|
|
VRBase = MRI->createVirtualRegister(TRC);
|
|
|
|
// Create the extract_subreg machine instruction.
|
|
BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
|
|
TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx);
|
|
}
|
|
} else if (Opc == TargetOpcode::INSERT_SUBREG ||
|
|
Opc == TargetOpcode::SUBREG_TO_REG) {
|
|
SDValue N0 = Node->getOperand(0);
|
|
SDValue N1 = Node->getOperand(1);
|
|
SDValue N2 = Node->getOperand(2);
|
|
unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
|
|
|
|
// Figure out the register class to create for the destreg. It should be
|
|
// the largest legal register class supporting SubIdx sub-registers.
|
|
// RegisterCoalescer will constrain it further if it decides to eliminate
|
|
// the INSERT_SUBREG instruction.
|
|
//
|
|
// %dst = INSERT_SUBREG %src, %sub, SubIdx
|
|
//
|
|
// is lowered by TwoAddressInstructionPass to:
|
|
//
|
|
// %dst = COPY %src
|
|
// %dst:SubIdx = COPY %sub
|
|
//
|
|
// There is no constraint on the %src register class.
|
|
//
|
|
const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getValueType(0));
|
|
SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
|
|
assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
|
|
|
|
if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
|
|
VRBase = MRI->createVirtualRegister(SRC);
|
|
|
|
// Create the insert_subreg or subreg_to_reg machine instruction.
|
|
MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc));
|
|
MI->addOperand(MachineOperand::CreateReg(VRBase, true));
|
|
|
|
// If creating a subreg_to_reg, then the first input operand
|
|
// is an implicit value immediate, otherwise it's a register
|
|
if (Opc == TargetOpcode::SUBREG_TO_REG) {
|
|
const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
|
|
MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue()));
|
|
} else
|
|
AddOperand(MI, N0, 0, 0, VRBaseMap, /*IsDebug=*/false,
|
|
IsClone, IsCloned);
|
|
// Add the subregster being inserted
|
|
AddOperand(MI, N1, 0, 0, VRBaseMap, /*IsDebug=*/false,
|
|
IsClone, IsCloned);
|
|
MI->addOperand(MachineOperand::CreateImm(SubIdx));
|
|
MBB->insert(InsertPos, MI);
|
|
} else
|
|
llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
|
|
|
|
SDValue Op(Node, 0);
|
|
bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
|
|
(void)isNew; // Silence compiler warning.
|
|
assert(isNew && "Node emitted out of order - early");
|
|
}
|
|
|
|
/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
|
|
/// COPY_TO_REGCLASS is just a normal copy, except that the destination
|
|
/// register is constrained to be in a particular register class.
|
|
///
|
|
void
|
|
InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
|
|
DenseMap<SDValue, unsigned> &VRBaseMap) {
|
|
unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
|
|
|
|
// Create the new VReg in the destination class and emit a copy.
|
|
unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
|
|
const TargetRegisterClass *DstRC =
|
|
TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
|
|
unsigned NewVReg = MRI->createVirtualRegister(DstRC);
|
|
BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
|
|
NewVReg).addReg(VReg);
|
|
|
|
SDValue Op(Node, 0);
|
|
bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
|
|
(void)isNew; // Silence compiler warning.
|
|
assert(isNew && "Node emitted out of order - early");
|
|
}
|
|
|
|
/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
|
|
///
|
|
void InstrEmitter::EmitRegSequence(SDNode *Node,
|
|
DenseMap<SDValue, unsigned> &VRBaseMap,
|
|
bool IsClone, bool IsCloned) {
|
|
unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
|
|
const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
|
|
unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
|
|
MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
|
|
TII->get(TargetOpcode::REG_SEQUENCE), NewVReg);
|
|
unsigned NumOps = Node->getNumOperands();
|
|
assert((NumOps & 1) == 1 &&
|
|
"REG_SEQUENCE must have an odd number of operands!");
|
|
const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
|
|
for (unsigned i = 1; i != NumOps; ++i) {
|
|
SDValue Op = Node->getOperand(i);
|
|
if ((i & 1) == 0) {
|
|
RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
|
|
// Skip physical registers as they don't have a vreg to get and we'll
|
|
// insert copies for them in TwoAddressInstructionPass anyway.
|
|
if (!R || !TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
|
|
unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
|
|
unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
|
|
const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
|
|
const TargetRegisterClass *SRC =
|
|
TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
|
|
if (SRC && SRC != RC) {
|
|
MRI->setRegClass(NewVReg, SRC);
|
|
RC = SRC;
|
|
}
|
|
}
|
|
}
|
|
AddOperand(MI, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
|
|
IsClone, IsCloned);
|
|
}
|
|
|
|
MBB->insert(InsertPos, MI);
|
|
SDValue Op(Node, 0);
|
|
bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
|
|
(void)isNew; // Silence compiler warning.
|
|
assert(isNew && "Node emitted out of order - early");
|
|
}
|
|
|
|
/// EmitDbgValue - Generate machine instruction for a dbg_value node.
|
|
///
|
|
MachineInstr *
|
|
InstrEmitter::EmitDbgValue(SDDbgValue *SD,
|
|
DenseMap<SDValue, unsigned> &VRBaseMap) {
|
|
uint64_t Offset = SD->getOffset();
|
|
MDNode* MDPtr = SD->getMDPtr();
|
|
DebugLoc DL = SD->getDebugLoc();
|
|
|
|
if (SD->getKind() == SDDbgValue::FRAMEIX) {
|
|
// Stack address; this needs to be lowered in target-dependent fashion.
|
|
// EmitTargetCodeForFrameDebugValue is responsible for allocation.
|
|
unsigned FrameIx = SD->getFrameIx();
|
|
return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL);
|
|
}
|
|
// Otherwise, we're going to create an instruction here.
|
|
const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
|
|
MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
|
|
if (SD->getKind() == SDDbgValue::SDNODE) {
|
|
SDNode *Node = SD->getSDNode();
|
|
SDValue Op = SDValue(Node, SD->getResNo());
|
|
// It's possible we replaced this SDNode with other(s) and therefore
|
|
// didn't generate code for it. It's better to catch these cases where
|
|
// they happen and transfer the debug info, but trying to guarantee that
|
|
// in all cases would be very fragile; this is a safeguard for any
|
|
// that were missed.
|
|
DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
|
|
if (I==VRBaseMap.end())
|
|
MIB.addReg(0U); // undef
|
|
else
|
|
AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
|
|
/*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
|
|
} else if (SD->getKind() == SDDbgValue::CONST) {
|
|
const Value *V = SD->getConst();
|
|
if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
|
|
if (CI->getBitWidth() > 64)
|
|
MIB.addCImm(CI);
|
|
else
|
|
MIB.addImm(CI->getSExtValue());
|
|
} else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
|
|
MIB.addFPImm(CF);
|
|
} else {
|
|
// Could be an Undef. In any case insert an Undef so we can see what we
|
|
// dropped.
|
|
MIB.addReg(0U);
|
|
}
|
|
} else {
|
|
// Insert an Undef so we can see what we dropped.
|
|
MIB.addReg(0U);
|
|
}
|
|
|
|
MIB.addImm(Offset).addMetadata(MDPtr);
|
|
return &*MIB;
|
|
}
|
|
|
|
/// EmitMachineNode - Generate machine code for a target-specific node and
|
|
/// needed dependencies.
|
|
///
|
|
void InstrEmitter::
|
|
EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
|
|
DenseMap<SDValue, unsigned> &VRBaseMap) {
|
|
unsigned Opc = Node->getMachineOpcode();
|
|
|
|
// Handle subreg insert/extract specially
|
|
if (Opc == TargetOpcode::EXTRACT_SUBREG ||
|
|
Opc == TargetOpcode::INSERT_SUBREG ||
|
|
Opc == TargetOpcode::SUBREG_TO_REG) {
|
|
EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
|
|
return;
|
|
}
|
|
|
|
// Handle COPY_TO_REGCLASS specially.
|
|
if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
|
|
EmitCopyToRegClassNode(Node, VRBaseMap);
|
|
return;
|
|
}
|
|
|
|
// Handle REG_SEQUENCE specially.
|
|
if (Opc == TargetOpcode::REG_SEQUENCE) {
|
|
EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
|
|
return;
|
|
}
|
|
|
|
if (Opc == TargetOpcode::IMPLICIT_DEF)
|
|
// We want a unique VR for each IMPLICIT_DEF use.
|
|
return;
|
|
|
|
const MCInstrDesc &II = TII->get(Opc);
|
|
unsigned NumResults = CountResults(Node);
|
|
unsigned NumImpUses = 0;
|
|
unsigned NodeOperands =
|
|
countOperands(Node, II.getNumOperands() - II.getNumDefs(), NumImpUses);
|
|
bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0;
|
|
#ifndef NDEBUG
|
|
unsigned NumMIOperands = NodeOperands + NumResults;
|
|
if (II.isVariadic())
|
|
assert(NumMIOperands >= II.getNumOperands() &&
|
|
"Too few operands for a variadic node!");
|
|
else
|
|
assert(NumMIOperands >= II.getNumOperands() &&
|
|
NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +
|
|
NumImpUses &&
|
|
"#operands for dag node doesn't match .td file!");
|
|
#endif
|
|
|
|
// Create the new machine instruction.
|
|
MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II);
|
|
|
|
// Add result register values for things that are defined by this
|
|
// instruction.
|
|
if (NumResults)
|
|
CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap);
|
|
|
|
// Emit all of the actual operands of this instruction, adding them to the
|
|
// instruction as appropriate.
|
|
bool HasOptPRefs = II.getNumDefs() > NumResults;
|
|
assert((!HasOptPRefs || !HasPhysRegOuts) &&
|
|
"Unable to cope with optional defs and phys regs defs!");
|
|
unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0;
|
|
for (unsigned i = NumSkip; i != NodeOperands; ++i)
|
|
AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II,
|
|
VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
|
|
|
|
// Transfer all of the memory reference descriptions of this instruction.
|
|
MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
|
|
cast<MachineSDNode>(Node)->memoperands_end());
|
|
|
|
// Insert the instruction into position in the block. This needs to
|
|
// happen before any custom inserter hook is called so that the
|
|
// hook knows where in the block to insert the replacement code.
|
|
MBB->insert(InsertPos, MI);
|
|
|
|
// The MachineInstr may also define physregs instead of virtregs. These
|
|
// physreg values can reach other instructions in different ways:
|
|
//
|
|
// 1. When there is a use of a Node value beyond the explicitly defined
|
|
// virtual registers, we emit a CopyFromReg for one of the implicitly
|
|
// defined physregs. This only happens when HasPhysRegOuts is true.
|
|
//
|
|
// 2. A CopyFromReg reading a physreg may be glued to this instruction.
|
|
//
|
|
// 3. A glued instruction may implicitly use a physreg.
|
|
//
|
|
// 4. A glued instruction may use a RegisterSDNode operand.
|
|
//
|
|
// Collect all the used physreg defs, and make sure that any unused physreg
|
|
// defs are marked as dead.
|
|
SmallVector<unsigned, 8> UsedRegs;
|
|
|
|
// Additional results must be physical register defs.
|
|
if (HasPhysRegOuts) {
|
|
for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
|
|
unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
|
|
if (!Node->hasAnyUseOfValue(i))
|
|
continue;
|
|
// This implicitly defined physreg has a use.
|
|
UsedRegs.push_back(Reg);
|
|
EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
|
|
}
|
|
}
|
|
|
|
// Scan the glue chain for any used physregs.
|
|
if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
|
|
for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
|
|
if (F->getOpcode() == ISD::CopyFromReg) {
|
|
UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
|
|
continue;
|
|
} else if (F->getOpcode() == ISD::CopyToReg) {
|
|
// Skip CopyToReg nodes that are internal to the glue chain.
|
|
continue;
|
|
}
|
|
// Collect declared implicit uses.
|
|
const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
|
|
UsedRegs.append(MCID.getImplicitUses(),
|
|
MCID.getImplicitUses() + MCID.getNumImplicitUses());
|
|
// In addition to declared implicit uses, we must also check for
|
|
// direct RegisterSDNode operands.
|
|
for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
|
|
if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
|
|
unsigned Reg = R->getReg();
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg))
|
|
UsedRegs.push_back(Reg);
|
|
}
|
|
}
|
|
}
|
|
|
|
// Finally mark unused registers as dead.
|
|
if (!UsedRegs.empty() || II.getImplicitDefs())
|
|
MI->setPhysRegsDeadExcept(UsedRegs, *TRI);
|
|
|
|
// Run post-isel target hook to adjust this instruction if needed.
|
|
#ifdef NDEBUG
|
|
if (II.hasPostISelHook())
|
|
#endif
|
|
TLI->AdjustInstrPostInstrSelection(MI, Node);
|
|
}
|
|
|
|
/// EmitSpecialNode - Generate machine code for a target-independent node and
|
|
/// needed dependencies.
|
|
void InstrEmitter::
|
|
EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
|
|
DenseMap<SDValue, unsigned> &VRBaseMap) {
|
|
switch (Node->getOpcode()) {
|
|
default:
|
|
#ifndef NDEBUG
|
|
Node->dump();
|
|
#endif
|
|
llvm_unreachable("This target-independent node should have been selected!");
|
|
case ISD::EntryToken:
|
|
llvm_unreachable("EntryToken should have been excluded from the schedule!");
|
|
case ISD::MERGE_VALUES:
|
|
case ISD::TokenFactor: // fall thru
|
|
break;
|
|
case ISD::CopyToReg: {
|
|
unsigned SrcReg;
|
|
SDValue SrcVal = Node->getOperand(2);
|
|
if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
|
|
SrcReg = R->getReg();
|
|
else
|
|
SrcReg = getVR(SrcVal, VRBaseMap);
|
|
|
|
unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
|
|
if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
|
|
break;
|
|
|
|
BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
|
|
DestReg).addReg(SrcReg);
|
|
break;
|
|
}
|
|
case ISD::CopyFromReg: {
|
|
unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
|
|
EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
|
|
break;
|
|
}
|
|
case ISD::EH_LABEL: {
|
|
MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel();
|
|
BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
|
|
TII->get(TargetOpcode::EH_LABEL)).addSym(S);
|
|
break;
|
|
}
|
|
|
|
case ISD::LIFETIME_START:
|
|
case ISD::LIFETIME_END: {
|
|
unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ?
|
|
TargetOpcode::LIFETIME_START : TargetOpcode::LIFETIME_END;
|
|
|
|
FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Node->getOperand(1));
|
|
BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
|
|
.addFrameIndex(FI->getIndex());
|
|
break;
|
|
}
|
|
|
|
case ISD::INLINEASM: {
|
|
unsigned NumOps = Node->getNumOperands();
|
|
if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
|
|
--NumOps; // Ignore the glue operand.
|
|
|
|
// Create the inline asm machine instruction.
|
|
MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
|
|
TII->get(TargetOpcode::INLINEASM));
|
|
|
|
// Add the asm string as an external symbol operand.
|
|
SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
|
|
const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
|
|
MI->addOperand(MachineOperand::CreateES(AsmStr));
|
|
|
|
// Add the HasSideEffect and isAlignStack bits.
|
|
int64_t ExtraInfo =
|
|
cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
|
|
getZExtValue();
|
|
MI->addOperand(MachineOperand::CreateImm(ExtraInfo));
|
|
|
|
// Remember to operand index of the group flags.
|
|
SmallVector<unsigned, 8> GroupIdx;
|
|
|
|
// Add all of the operand registers to the instruction.
|
|
for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
|
|
unsigned Flags =
|
|
cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
|
|
const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
|
|
|
|
GroupIdx.push_back(MI->getNumOperands());
|
|
MI->addOperand(MachineOperand::CreateImm(Flags));
|
|
++i; // Skip the ID value.
|
|
|
|
switch (InlineAsm::getKind(Flags)) {
|
|
default: llvm_unreachable("Bad flags!");
|
|
case InlineAsm::Kind_RegDef:
|
|
for (unsigned j = 0; j != NumVals; ++j, ++i) {
|
|
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
|
|
// FIXME: Add dead flags for physical and virtual registers defined.
|
|
// For now, mark physical register defs as implicit to help fast
|
|
// regalloc. This makes inline asm look a lot like calls.
|
|
MI->addOperand(MachineOperand::CreateReg(Reg, true,
|
|
/*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg)));
|
|
}
|
|
break;
|
|
case InlineAsm::Kind_RegDefEarlyClobber:
|
|
case InlineAsm::Kind_Clobber:
|
|
for (unsigned j = 0; j != NumVals; ++j, ++i) {
|
|
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
|
|
MI->addOperand(MachineOperand::CreateReg(Reg, /*isDef=*/ true,
|
|
/*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg),
|
|
/*isKill=*/ false,
|
|
/*isDead=*/ false,
|
|
/*isUndef=*/false,
|
|
/*isEarlyClobber=*/ true));
|
|
}
|
|
break;
|
|
case InlineAsm::Kind_RegUse: // Use of register.
|
|
case InlineAsm::Kind_Imm: // Immediate.
|
|
case InlineAsm::Kind_Mem: // Addressing mode.
|
|
// The addressing mode has been selected, just add all of the
|
|
// operands to the machine instruction.
|
|
for (unsigned j = 0; j != NumVals; ++j, ++i)
|
|
AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap,
|
|
/*IsDebug=*/false, IsClone, IsCloned);
|
|
|
|
// Manually set isTied bits.
|
|
if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) {
|
|
unsigned DefGroup = 0;
|
|
if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
|
|
unsigned DefIdx = GroupIdx[DefGroup] + 1;
|
|
unsigned UseIdx = GroupIdx.back() + 1;
|
|
for (unsigned j = 0; j != NumVals; ++j)
|
|
MI->tieOperands(DefIdx + j, UseIdx + j);
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
// Get the mdnode from the asm if it exists and add it to the instruction.
|
|
SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
|
|
const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
|
|
if (MD)
|
|
MI->addOperand(MachineOperand::CreateMetadata(MD));
|
|
|
|
MBB->insert(InsertPos, MI);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
/// InstrEmitter - Construct an InstrEmitter and set it to start inserting
|
|
/// at the given position in the given block.
|
|
InstrEmitter::InstrEmitter(MachineBasicBlock *mbb,
|
|
MachineBasicBlock::iterator insertpos)
|
|
: MF(mbb->getParent()),
|
|
MRI(&MF->getRegInfo()),
|
|
TM(&MF->getTarget()),
|
|
TII(TM->getInstrInfo()),
|
|
TRI(TM->getRegisterInfo()),
|
|
TLI(TM->getTargetLowering()),
|
|
MBB(mbb), InsertPos(insertpos) {
|
|
}
|