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Switch to MCSuperRegIterator while we're there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157717 91177308-0d34-0410-b5e6-96231b3b80d8
333 lines
11 KiB
C++
333 lines
11 KiB
C++
//===-- HexagonFrameLowering.cpp - Define frame lowering ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonFrameLowering.h"
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#include "Hexagon.h"
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#include "HexagonInstrInfo.h"
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#include "HexagonRegisterInfo.h"
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#include "HexagonSubtarget.h"
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#include "HexagonTargetMachine.h"
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#include "HexagonMachineFunctionInfo.h"
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#include "llvm/Function.h"
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#include "llvm/Type.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/MC/MachineLocation.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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static cl::opt<bool> DisableDeallocRet(
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"disable-hexagon-dealloc-ret",
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cl::Hidden,
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cl::desc("Disable Dealloc Return for Hexagon target"));
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/// determineFrameLayout - Determine the size of the frame and maximum call
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/// frame size.
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void HexagonFrameLowering::determineFrameLayout(MachineFunction &MF) const {
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MachineFrameInfo *MFI = MF.getFrameInfo();
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// Get the number of bytes to allocate from the FrameInfo.
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unsigned FrameSize = MFI->getStackSize();
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// Get the alignments provided by the target.
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unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
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// Get the maximum call frame size of all the calls.
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unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
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// If we have dynamic alloca then maxCallFrameSize needs to be aligned so
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// that allocations will be aligned.
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if (MFI->hasVarSizedObjects())
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maxCallFrameSize = RoundUpToAlignment(maxCallFrameSize, TargetAlign);
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// Update maximum call frame size.
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MFI->setMaxCallFrameSize(maxCallFrameSize);
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// Include call frame size in total.
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FrameSize += maxCallFrameSize;
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// Make sure the frame is aligned.
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FrameSize = RoundUpToAlignment(FrameSize, TargetAlign);
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// Update frame info.
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MFI->setStackSize(FrameSize);
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}
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void HexagonFrameLowering::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineModuleInfo &MMI = MF.getMMI();
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MachineBasicBlock::iterator MBBI = MBB.begin();
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const HexagonRegisterInfo *QRI =
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static_cast<const HexagonRegisterInfo *>(MF.getTarget().getRegisterInfo());
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DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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determineFrameLayout(MF);
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// Check if frame moves are needed for EH.
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bool needsFrameMoves = MMI.hasDebugInfo() ||
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!MF.getFunction()->needsUnwindTableEntry();
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// Get the number of bytes to allocate from the FrameInfo.
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int NumBytes = (int) MFI->getStackSize();
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// LLVM expects allocframe not to be the first instruction in the
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// basic block.
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MachineBasicBlock::iterator InsertPt = MBB.begin();
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//
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// ALLOCA adjust regs. Iterate over ADJDYNALLOC nodes and change the offset.
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//
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HexagonMachineFunctionInfo *FuncInfo =
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MF.getInfo<HexagonMachineFunctionInfo>();
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const std::vector<MachineInstr*>& AdjustRegs =
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FuncInfo->getAllocaAdjustInsts();
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for (std::vector<MachineInstr*>::const_iterator i = AdjustRegs.begin(),
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e = AdjustRegs.end();
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i != e; ++i) {
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MachineInstr* MI = *i;
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assert((MI->getOpcode() == Hexagon::ADJDYNALLOC) &&
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"Expected adjust alloca node");
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MachineOperand& MO = MI->getOperand(2);
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assert(MO.isImm() && "Expected immediate");
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MO.setImm(MFI->getMaxCallFrameSize());
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}
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std::vector<MachineMove> &Moves = MMI.getFrameMoves();
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if (needsFrameMoves) {
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// Advance CFA. DW_CFA_def_cfa
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unsigned FPReg = QRI->getFrameRegister();
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unsigned RAReg = QRI->getRARegister();
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MachineLocation Dst(MachineLocation::VirtualFP);
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MachineLocation Src(FPReg, -8);
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Moves.push_back(MachineMove(0, Dst, Src));
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// R31 = (R31 - #4)
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MachineLocation LRDst(RAReg, -4);
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MachineLocation LRSrc(RAReg);
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Moves.push_back(MachineMove(0, LRDst, LRSrc));
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// R30 = (R30 - #8)
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MachineLocation SPDst(FPReg, -8);
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MachineLocation SPSrc(FPReg);
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Moves.push_back(MachineMove(0, SPDst, SPSrc));
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}
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//
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// Only insert ALLOCFRAME if we need to.
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//
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if (hasFP(MF)) {
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// Check for overflow.
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// Hexagon_TODO: Ugh! hardcoding. Is there an API that can be used?
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const int ALLOCFRAME_MAX = 16384;
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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if (NumBytes >= ALLOCFRAME_MAX) {
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// Emit allocframe(#0).
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BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(0);
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// Subtract offset from frame pointer.
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BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::CONST32_Int_Real),
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HEXAGON_RESERVED_REG_1).addImm(NumBytes);
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BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::SUB_rr),
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QRI->getStackRegister()).
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addReg(QRI->getStackRegister()).
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addReg(HEXAGON_RESERVED_REG_1);
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} else {
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BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(NumBytes);
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}
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}
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}
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// Returns true if MBB has a machine instructions that indicates a tail call
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// in the block.
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bool HexagonFrameLowering::hasTailCall(MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
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unsigned RetOpcode = MBBI->getOpcode();
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return RetOpcode == Hexagon::TCRETURNtg || RetOpcode == Hexagon::TCRETURNtext;}
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void HexagonFrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = prior(MBB.end());
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DebugLoc dl = MBBI->getDebugLoc();
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//
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// Only insert deallocframe if we need to.
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//
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if (hasFP(MF)) {
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MachineBasicBlock::iterator MBBI = prior(MBB.end());
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MachineBasicBlock::iterator MBBI_end = MBB.end();
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//
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// For Hexagon, we don't need the frame size.
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//
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MachineFrameInfo *MFI = MF.getFrameInfo();
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int NumBytes = (int) MFI->getStackSize();
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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// Replace 'jumpr r31' instruction with dealloc_return for V4 and higher
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// versions.
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if (STI.hasV4TOps() && MBBI->getOpcode() == Hexagon::JMPR
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&& !DisableDeallocRet) {
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// Remove jumpr node.
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MBB.erase(MBBI);
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// Add dealloc_return.
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BuildMI(MBB, MBBI_end, dl, TII.get(Hexagon::DEALLOC_RET_V4))
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.addImm(NumBytes);
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} else { // Add deallocframe for V2 and V3.
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BuildMI(MBB, MBBI, dl, TII.get(Hexagon::DEALLOCFRAME)).addImm(NumBytes);
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}
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}
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}
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bool HexagonFrameLowering::hasFP(const MachineFunction &MF) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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const HexagonMachineFunctionInfo *FuncInfo =
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MF.getInfo<HexagonMachineFunctionInfo>();
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return (MFI->hasCalls() || (MFI->getStackSize() > 0) ||
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FuncInfo->hasClobberLR() );
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}
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static inline
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unsigned uniqueSuperReg(unsigned Reg, const TargetRegisterInfo *TRI) {
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MCSuperRegIterator SRI(Reg, TRI);
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assert(SRI.isValid() && "Expected a superreg");
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unsigned SuperReg = *SRI;
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++SRI;
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assert(!SRI.isValid() && "Expected exactly one superreg");
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return SuperReg;
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}
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bool
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HexagonFrameLowering::spillCalleeSavedRegisters(
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const {
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MachineFunction *MF = MBB.getParent();
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const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
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if (CSI.empty()) {
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return false;
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}
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// We can only schedule double loads if we spill contiguous callee-saved regs
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// For instance, we cannot scheduled double-word loads if we spill r24,
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// r26, and r27.
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// Hexagon_TODO: We can try to double-word align odd registers for -O2 and
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// above.
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bool ContiguousRegs = true;
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for (unsigned i = 0; i < CSI.size(); ++i) {
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unsigned Reg = CSI[i].getReg();
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//
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// Check if we can use a double-word store.
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//
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unsigned SuperReg = uniqueSuperReg(Reg, TRI);
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bool CanUseDblStore = false;
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const TargetRegisterClass* SuperRegClass = 0;
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if (ContiguousRegs && (i < CSI.size()-1)) {
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unsigned SuperRegNext = uniqueSuperReg(CSI[i+1].getReg(), TRI);
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SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg);
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CanUseDblStore = (SuperRegNext == SuperReg);
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}
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if (CanUseDblStore) {
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TII.storeRegToStackSlot(MBB, MI, SuperReg, true,
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CSI[i+1].getFrameIdx(), SuperRegClass, TRI);
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MBB.addLiveIn(SuperReg);
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++i;
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} else {
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// Cannot use a double-word store.
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ContiguousRegs = false;
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const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
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TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(), RC,
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TRI);
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MBB.addLiveIn(Reg);
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}
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}
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return true;
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}
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bool HexagonFrameLowering::restoreCalleeSavedRegisters(
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const {
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MachineFunction *MF = MBB.getParent();
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const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
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if (CSI.empty()) {
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return false;
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}
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// We can only schedule double loads if we spill contiguous callee-saved regs
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// For instance, we cannot scheduled double-word loads if we spill r24,
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// r26, and r27.
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// Hexagon_TODO: We can try to double-word align odd registers for -O2 and
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// above.
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bool ContiguousRegs = true;
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for (unsigned i = 0; i < CSI.size(); ++i) {
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unsigned Reg = CSI[i].getReg();
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//
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// Check if we can use a double-word load.
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//
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unsigned SuperReg = uniqueSuperReg(Reg, TRI);
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const TargetRegisterClass* SuperRegClass = 0;
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bool CanUseDblLoad = false;
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if (ContiguousRegs && (i < CSI.size()-1)) {
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unsigned SuperRegNext = uniqueSuperReg(CSI[i+1].getReg(), TRI);
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SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg);
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CanUseDblLoad = (SuperRegNext == SuperReg);
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}
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if (CanUseDblLoad) {
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TII.loadRegFromStackSlot(MBB, MI, SuperReg, CSI[i+1].getFrameIdx(),
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SuperRegClass, TRI);
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MBB.addLiveIn(SuperReg);
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++i;
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} else {
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// Cannot use a double-word load.
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ContiguousRegs = false;
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const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
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TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
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MBB.addLiveIn(Reg);
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}
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}
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return true;
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}
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int HexagonFrameLowering::getFrameIndexOffset(const MachineFunction &MF,
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int FI) const {
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return MF.getFrameInfo()->getObjectOffset(FI);
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}
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