mirror of
https://github.com/c64scene-ar/llvm-6502.git
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fc1a161d76
Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161888 91177308-0d34-0410-b5e6-96231b3b80d8
524 lines
19 KiB
C++
524 lines
19 KiB
C++
//===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the Mips Disassembler.
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//
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//===----------------------------------------------------------------------===//
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#include "Mips.h"
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#include "MipsSubtarget.h"
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#include "MipsRegisterInfo.h"
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#include "llvm/MC/EDInstInfo.h"
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#include "llvm/MC/MCDisassembler.h"
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#include "llvm/MC/MCFixedLenDisassembler.h"
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#include "llvm/Support/MemoryObject.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Support/MathExtras.h"
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#include "MipsGenEDInfo.inc"
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using namespace llvm;
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typedef MCDisassembler::DecodeStatus DecodeStatus;
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namespace {
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/// MipsDisassemblerBase - a disasembler class for Mips.
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class MipsDisassemblerBase : public MCDisassembler {
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public:
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/// Constructor - Initializes the disassembler.
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///
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MipsDisassemblerBase(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
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bool bigEndian) :
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MCDisassembler(STI), RegInfo(Info), isBigEndian(bigEndian) {}
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virtual ~MipsDisassemblerBase() {}
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/// getEDInfo - See MCDisassembler.
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const EDInstInfo *getEDInfo() const;
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const MCRegisterInfo *getRegInfo() const { return RegInfo; }
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private:
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const MCRegisterInfo *RegInfo;
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protected:
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bool isBigEndian;
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};
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/// MipsDisassembler - a disasembler class for Mips32.
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class MipsDisassembler : public MipsDisassemblerBase {
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public:
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/// Constructor - Initializes the disassembler.
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///
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MipsDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
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bool bigEndian) :
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MipsDisassemblerBase(STI, Info, bigEndian) {}
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/// getInstruction - See MCDisassembler.
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virtual DecodeStatus getInstruction(MCInst &instr,
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uint64_t &size,
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const MemoryObject ®ion,
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uint64_t address,
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raw_ostream &vStream,
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raw_ostream &cStream) const;
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};
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/// Mips64Disassembler - a disasembler class for Mips64.
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class Mips64Disassembler : public MipsDisassemblerBase {
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public:
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/// Constructor - Initializes the disassembler.
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///
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Mips64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
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bool bigEndian) :
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MipsDisassemblerBase(STI, Info, bigEndian) {}
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/// getInstruction - See MCDisassembler.
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virtual DecodeStatus getInstruction(MCInst &instr,
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uint64_t &size,
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const MemoryObject ®ion,
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uint64_t address,
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raw_ostream &vStream,
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raw_ostream &cStream) const;
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};
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} // end anonymous namespace
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const EDInstInfo *MipsDisassemblerBase::getEDInfo() const {
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return instInfoMips;
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}
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// Forward declare these because the autogenerated code will reference them.
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// Definitions are further down.
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static DecodeStatus DecodeCPU64RegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeCPURegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeBranchTarget(MCInst &Inst,
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unsigned Offset,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeBC1(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeJumpTarget(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeMem(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeSimm16(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeCondCode(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeInsSize(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeExtSize(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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namespace llvm {
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extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
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TheMips64elTarget;
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}
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static MCDisassembler *createMipsDisassembler(
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const Target &T,
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const MCSubtargetInfo &STI) {
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return new MipsDisassembler(STI, T.createMCRegInfo(""), true);
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}
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static MCDisassembler *createMipselDisassembler(
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const Target &T,
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const MCSubtargetInfo &STI) {
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return new MipsDisassembler(STI, T.createMCRegInfo(""), false);
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}
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static MCDisassembler *createMips64Disassembler(
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const Target &T,
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const MCSubtargetInfo &STI) {
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return new Mips64Disassembler(STI, T.createMCRegInfo(""), true);
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}
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static MCDisassembler *createMips64elDisassembler(
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const Target &T,
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const MCSubtargetInfo &STI) {
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return new Mips64Disassembler(STI, T.createMCRegInfo(""), false);
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}
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extern "C" void LLVMInitializeMipsDisassembler() {
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// Register the disassembler.
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TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
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createMipsDisassembler);
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TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
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createMipselDisassembler);
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TargetRegistry::RegisterMCDisassembler(TheMips64Target,
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createMips64Disassembler);
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TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
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createMips64elDisassembler);
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}
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#include "MipsGenDisassemblerTables.inc"
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/// readInstruction - read four bytes from the MemoryObject
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/// and return 32 bit word sorted according to the given endianess
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static DecodeStatus readInstruction32(const MemoryObject ®ion,
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uint64_t address,
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uint64_t &size,
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uint32_t &insn,
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bool isBigEndian) {
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uint8_t Bytes[4];
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// We want to read exactly 4 Bytes of data.
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if (region.readBytes(address, 4, (uint8_t*)Bytes, NULL) == -1) {
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size = 0;
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return MCDisassembler::Fail;
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}
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if (isBigEndian) {
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// Encoded as a big-endian 32-bit word in the stream.
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insn = (Bytes[3] << 0) |
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(Bytes[2] << 8) |
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(Bytes[1] << 16) |
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(Bytes[0] << 24);
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}
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else {
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// Encoded as a small-endian 32-bit word in the stream.
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insn = (Bytes[0] << 0) |
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(Bytes[1] << 8) |
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(Bytes[2] << 16) |
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(Bytes[3] << 24);
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}
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return MCDisassembler::Success;
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}
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DecodeStatus
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MipsDisassembler::getInstruction(MCInst &instr,
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uint64_t &Size,
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const MemoryObject &Region,
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uint64_t Address,
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raw_ostream &vStream,
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raw_ostream &cStream) const {
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uint32_t Insn;
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DecodeStatus Result = readInstruction32(Region, Address, Size,
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Insn, isBigEndian);
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if (Result == MCDisassembler::Fail)
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return MCDisassembler::Fail;
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// Calling the auto-generated decoder function.
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Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
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this, STI);
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if (Result != MCDisassembler::Fail) {
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Size = 4;
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return Result;
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}
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return MCDisassembler::Fail;
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}
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DecodeStatus
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Mips64Disassembler::getInstruction(MCInst &instr,
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uint64_t &Size,
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const MemoryObject &Region,
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uint64_t Address,
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raw_ostream &vStream,
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raw_ostream &cStream) const {
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uint32_t Insn;
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DecodeStatus Result = readInstruction32(Region, Address, Size,
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Insn, isBigEndian);
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if (Result == MCDisassembler::Fail)
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return MCDisassembler::Fail;
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// Calling the auto-generated decoder function.
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Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
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this, STI);
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if (Result != MCDisassembler::Fail) {
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Size = 4;
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return Result;
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}
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// If we fail to decode in Mips64 decoder space we can try in Mips32
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Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
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this, STI);
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if (Result != MCDisassembler::Fail) {
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Size = 4;
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return Result;
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}
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return MCDisassembler::Fail;
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}
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static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
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const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
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return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
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}
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static DecodeStatus DecodeCPU64RegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned Reg = getReg(Decoder, Mips::CPU64RegsRegClassID, RegNo);
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeCPURegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned Reg = getReg(Decoder, Mips::CPURegsRegClassID, RegNo);
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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Inst.addOperand(MCOperand::CreateReg(RegNo));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeMem(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder) {
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int Offset = SignExtend32<16>(Insn & 0xffff);
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unsigned Reg = fieldFromInstruction(Insn, 16, 5);
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unsigned Base = fieldFromInstruction(Insn, 21, 5);
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Reg = getReg(Decoder, Mips::CPURegsRegClassID, Reg);
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Base = getReg(Decoder, Mips::CPURegsRegClassID, Base);
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if(Inst.getOpcode() == Mips::SC){
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Inst.addOperand(MCOperand::CreateReg(Reg));
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}
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Inst.addOperand(MCOperand::CreateReg(Reg));
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Inst.addOperand(MCOperand::CreateReg(Base));
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Inst.addOperand(MCOperand::CreateImm(Offset));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFMem(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder) {
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int Offset = SignExtend32<16>(Insn & 0xffff);
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unsigned Reg = fieldFromInstruction(Insn, 16, 5);
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unsigned Base = fieldFromInstruction(Insn, 21, 5);
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Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
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Base = getReg(Decoder, Mips::CPURegsRegClassID, Base);
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Inst.addOperand(MCOperand::CreateReg(Reg));
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Inst.addOperand(MCOperand::CreateReg(Base));
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Inst.addOperand(MCOperand::CreateImm(Offset));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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// Currently only hardware register 29 is supported.
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if (RegNo != 29)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeCondCode(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder) {
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int CondCode = Insn & 0xf;
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Inst.addOperand(MCOperand::CreateImm(CondCode));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 30 || RegNo %2)
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return MCDisassembler::Fail;
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;
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unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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//Currently only hardware register 29 is supported
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if (RegNo != 29)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::CreateReg(Mips::HWR29_64));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeBranchTarget(MCInst &Inst,
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unsigned Offset,
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uint64_t Address,
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const void *Decoder) {
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unsigned BranchOffset = Offset & 0xffff;
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BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4;
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Inst.addOperand(MCOperand::CreateImm(BranchOffset));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeBC1(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder) {
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unsigned BranchOffset = Insn & 0xffff;
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BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4;
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Inst.addOperand(MCOperand::CreateImm(BranchOffset));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeJumpTarget(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder) {
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unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
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Inst.addOperand(MCOperand::CreateImm(JumpOffset));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeSimm16(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder) {
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Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
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return MCDisassembler::Success;
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}
|
|
|
|
static DecodeStatus DecodeInsSize(MCInst &Inst,
|
|
unsigned Insn,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
// First we need to grab the pos(lsb) from MCInst.
|
|
int Pos = Inst.getOperand(2).getImm();
|
|
int Size = (int) Insn - Pos + 1;
|
|
Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeExtSize(MCInst &Inst,
|
|
unsigned Insn,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
int Size = (int) Insn + 1;
|
|
Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
|
|
return MCDisassembler::Success;
|
|
}
|