mirror of
https://github.com/c64scene-ar/llvm-6502.git
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fc4eafa0f4
the temporary register that was used to load the immediate. Currently, it always returns register $at, but this will change if, in the future, we decide to use another register. No changes in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162417 91177308-0d34-0410-b5e6-96231b3b80d8
360 lines
13 KiB
C++
360 lines
13 KiB
C++
//===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips32/64 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsSEInstrInfo.h"
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#include "MipsTargetMachine.h"
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#include "MipsMachineFunction.h"
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#include "InstPrinter/MipsInstPrinter.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/ADT/STLExtras.h"
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using namespace llvm;
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MipsSEInstrInfo::MipsSEInstrInfo(MipsTargetMachine &tm)
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: MipsInstrInfo(tm,
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tm.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J),
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RI(*tm.getSubtargetImpl(), *this),
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IsN64(tm.getSubtarget<MipsSubtarget>().isABI_N64()) {}
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const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
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return RI;
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}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned MipsSEInstrInfo::
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isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
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{
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unsigned Opc = MI->getOpcode();
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if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) ||
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(Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) ||
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(Opc == Mips::LDC1) || (Opc == Mips::LDC164) ||
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(Opc == Mips::LDC164_P8)) {
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if ((MI->getOperand(1).isFI()) && // is a stack slot
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(MI->getOperand(2).isImm()) && // the imm is zero
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(isZeroImm(MI->getOperand(2)))) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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}
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned MipsSEInstrInfo::
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isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
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{
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unsigned Opc = MI->getOpcode();
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if ((Opc == Mips::SW) || (Opc == Mips::SW_P8) || (Opc == Mips::SD) ||
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(Opc == Mips::SD_P8) || (Opc == Mips::SWC1) || (Opc == Mips::SWC1_P8) ||
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(Opc == Mips::SDC1) || (Opc == Mips::SDC164) ||
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(Opc == Mips::SDC164_P8)) {
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if ((MI->getOperand(1).isFI()) && // is a stack slot
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(MI->getOperand(2).isImm()) && // the imm is zero
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(isZeroImm(MI->getOperand(2)))) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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}
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return 0;
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}
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void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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unsigned Opc = 0, ZeroReg = 0;
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if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
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if (Mips::CPURegsRegClass.contains(SrcReg))
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Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
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else if (Mips::CCRRegClass.contains(SrcReg))
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Opc = Mips::CFC1;
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else if (Mips::FGR32RegClass.contains(SrcReg))
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Opc = Mips::MFC1;
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else if (SrcReg == Mips::HI)
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Opc = Mips::MFHI, SrcReg = 0;
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else if (SrcReg == Mips::LO)
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Opc = Mips::MFLO, SrcReg = 0;
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}
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else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg.
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if (Mips::CCRRegClass.contains(DestReg))
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Opc = Mips::CTC1;
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else if (Mips::FGR32RegClass.contains(DestReg))
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Opc = Mips::MTC1;
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else if (DestReg == Mips::HI)
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Opc = Mips::MTHI, DestReg = 0;
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else if (DestReg == Mips::LO)
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Opc = Mips::MTLO, DestReg = 0;
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}
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else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
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Opc = Mips::FMOV_S;
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else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
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Opc = Mips::FMOV_D32;
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else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
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Opc = Mips::FMOV_D64;
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else if (Mips::CCRRegClass.contains(DestReg, SrcReg))
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Opc = Mips::MOVCCRToCCR;
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else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg.
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if (Mips::CPU64RegsRegClass.contains(SrcReg))
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Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
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else if (SrcReg == Mips::HI64)
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Opc = Mips::MFHI64, SrcReg = 0;
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else if (SrcReg == Mips::LO64)
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Opc = Mips::MFLO64, SrcReg = 0;
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else if (Mips::FGR64RegClass.contains(SrcReg))
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Opc = Mips::DMFC1;
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}
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else if (Mips::CPU64RegsRegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
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if (DestReg == Mips::HI64)
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Opc = Mips::MTHI64, DestReg = 0;
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else if (DestReg == Mips::LO64)
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Opc = Mips::MTLO64, DestReg = 0;
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else if (Mips::FGR64RegClass.contains(DestReg))
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Opc = Mips::DMTC1;
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}
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assert(Opc && "Cannot copy registers");
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MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
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if (DestReg)
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MIB.addReg(DestReg, RegState::Define);
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if (ZeroReg)
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MIB.addReg(ZeroReg);
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if (SrcReg)
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MIB.addReg(SrcReg, getKillRegState(KillSrc));
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}
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void MipsSEInstrInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
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unsigned Opc = 0;
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if (Mips::CPURegsRegClass.hasSubClassEq(RC))
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Opc = IsN64 ? Mips::SW_P8 : Mips::SW;
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else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC))
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Opc = IsN64 ? Mips::SD_P8 : Mips::SD;
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else if (Mips::FGR32RegClass.hasSubClassEq(RC))
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Opc = IsN64 ? Mips::SWC1_P8 : Mips::SWC1;
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else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
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Opc = Mips::SDC1;
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else if (Mips::FGR64RegClass.hasSubClassEq(RC))
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Opc = IsN64 ? Mips::SDC164_P8 : Mips::SDC164;
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assert(Opc && "Register class not handled!");
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BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
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}
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void MipsSEInstrInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const
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{
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
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unsigned Opc = 0;
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if (Mips::CPURegsRegClass.hasSubClassEq(RC))
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Opc = IsN64 ? Mips::LW_P8 : Mips::LW;
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else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC))
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Opc = IsN64 ? Mips::LD_P8 : Mips::LD;
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else if (Mips::FGR32RegClass.hasSubClassEq(RC))
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Opc = IsN64 ? Mips::LWC1_P8 : Mips::LWC1;
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else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
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Opc = Mips::LDC1;
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else if (Mips::FGR64RegClass.hasSubClassEq(RC))
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Opc = IsN64 ? Mips::LDC164_P8 : Mips::LDC164;
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assert(Opc && "Register class not handled!");
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BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0)
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.addMemOperand(MMO);
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}
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bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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MachineBasicBlock &MBB = *MI->getParent();
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switch(MI->getDesc().getOpcode()) {
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default:
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return false;
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case Mips::RetRA:
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ExpandRetRA(MBB, MI, Mips::RET);
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break;
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case Mips::BuildPairF64:
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ExpandBuildPairF64(MBB, MI);
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break;
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case Mips::ExtractElementF64:
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ExpandExtractElementF64(MBB, MI);
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break;
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}
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MBB.erase(MI);
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return true;
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}
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/// GetOppositeBranchOpc - Return the inverse of the specified
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/// opcode, e.g. turning BEQ to BNE.
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unsigned MipsSEInstrInfo::GetOppositeBranchOpc(unsigned Opc) const {
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switch (Opc) {
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default: llvm_unreachable("Illegal opcode!");
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case Mips::BEQ: return Mips::BNE;
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case Mips::BNE: return Mips::BEQ;
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case Mips::BGTZ: return Mips::BLEZ;
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case Mips::BGEZ: return Mips::BLTZ;
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case Mips::BLTZ: return Mips::BGEZ;
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case Mips::BLEZ: return Mips::BGTZ;
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case Mips::BEQ64: return Mips::BNE64;
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case Mips::BNE64: return Mips::BEQ64;
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case Mips::BGTZ64: return Mips::BLEZ64;
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case Mips::BGEZ64: return Mips::BLTZ64;
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case Mips::BLTZ64: return Mips::BGEZ64;
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case Mips::BLEZ64: return Mips::BGTZ64;
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case Mips::BC1T: return Mips::BC1F;
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case Mips::BC1F: return Mips::BC1T;
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}
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}
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/// Adjust SP by Amount bytes.
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void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
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DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
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unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
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unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
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if (isInt<16>(Amount))// addi sp, sp, amount
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BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
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else { // Expand immediate that doesn't fit in 16-bit.
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MBB.getParent()->getInfo<MipsFunctionInfo>()->setEmitNOAT();
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unsigned Reg = loadImmediate(Amount, MBB, I, DL, 0);
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BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg);
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}
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}
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/// This function generates the sequence of instructions needed to get the
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/// result of adding register REG and immediate IMM.
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unsigned
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MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator II, DebugLoc DL,
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unsigned *NewImm) const {
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MipsAnalyzeImmediate AnalyzeImm;
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const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
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unsigned Size = STI.isABI_N64() ? 64 : 32;
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unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
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unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
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unsigned ATReg = STI.isABI_N64() ? Mips::AT_64 : Mips::AT;
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bool LastInstrIsADDiu = NewImm;
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const MipsAnalyzeImmediate::InstSeq &Seq =
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AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
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MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
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assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1)));
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// The first instruction can be a LUi, which is different from other
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// instructions (ADDiu, ORI and SLL) in that it does not have a register
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// operand.
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if (Inst->Opc == LUi)
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BuildMI(MBB, II, DL, get(LUi), ATReg)
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.addImm(SignExtend64<16>(Inst->ImmOpnd));
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else
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BuildMI(MBB, II, DL, get(Inst->Opc), ATReg).addReg(ZEROReg)
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.addImm(SignExtend64<16>(Inst->ImmOpnd));
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// Build the remaining instructions in Seq.
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for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst)
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BuildMI(MBB, II, DL, get(Inst->Opc), ATReg).addReg(ATReg)
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.addImm(SignExtend64<16>(Inst->ImmOpnd));
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if (LastInstrIsADDiu)
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*NewImm = Inst->ImmOpnd;
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return ATReg;
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}
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unsigned MipsSEInstrInfo::GetAnalyzableBrOpc(unsigned Opc) const {
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return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ ||
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Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ ||
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Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 ||
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Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
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Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B ||
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Opc == Mips::J) ?
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Opc : 0;
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}
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void MipsSEInstrInfo::ExpandRetRA(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned Opc) const {
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BuildMI(MBB, I, I->getDebugLoc(), get(Opc)).addReg(Mips::RA);
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}
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void MipsSEInstrInfo::ExpandExtractElementF64(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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unsigned DstReg = I->getOperand(0).getReg();
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unsigned SrcReg = I->getOperand(1).getReg();
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unsigned N = I->getOperand(2).getImm();
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const MCInstrDesc& Mfc1Tdd = get(Mips::MFC1);
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DebugLoc dl = I->getDebugLoc();
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assert(N < 2 && "Invalid immediate");
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unsigned SubIdx = N ? Mips::sub_fpodd : Mips::sub_fpeven;
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unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
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BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(SubReg);
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}
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void MipsSEInstrInfo::ExpandBuildPairF64(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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unsigned DstReg = I->getOperand(0).getReg();
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unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
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const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
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DebugLoc dl = I->getDebugLoc();
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const TargetRegisterInfo &TRI = getRegisterInfo();
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// mtc1 Lo, $fp
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// mtc1 Hi, $fp + 1
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BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpeven))
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.addReg(LoReg);
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BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpodd))
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.addReg(HiReg);
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}
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const MipsInstrInfo *llvm::createMipsSEInstrInfo(MipsTargetMachine &TM) {
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return new MipsSEInstrInfo(TM);
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}
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