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5b00ceaeea
Dynamic linking on PPC64 has had problems since we had to move the top-down hazard-detection logic post-ra. For dynamic linking to work there needs to be a nop placed after every call. It turns out that it is really hard to guarantee that nothing will be placed in between the call (bl) and the nop during post-ra scheduling. Previous attempts at fixing this by placing logic inside the hazard detector only partially worked. This is now fixed in a different way: call+nop codegen-only instructions. As far as CodeGen is concerned the pair is now a single instruction and cannot be split. This solution works much better than previous attempts. The scoreboard hazard detector is also renamed to be more generic, there is currently no cpu-specific logic in it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153816 91177308-0d34-0410-b5e6-96231b3b80d8
92 lines
3.3 KiB
C++
92 lines
3.3 KiB
C++
//===-- PPCHazardRecognizers.h - PowerPC Hazard Recognizers -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines hazard recognizers for scheduling on PowerPC processors.
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//
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//===----------------------------------------------------------------------===//
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#ifndef PPCHAZRECS_H
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#define PPCHAZRECS_H
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#include "PPCInstrInfo.h"
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#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
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#include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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namespace llvm {
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/// PPCScoreboardHazardRecognizer - This class implements a scoreboard-based
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/// hazard recognizer for generic PPC processors.
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class PPCScoreboardHazardRecognizer : public ScoreboardHazardRecognizer {
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const ScheduleDAG *DAG;
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public:
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PPCScoreboardHazardRecognizer(const InstrItineraryData *ItinData,
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const ScheduleDAG *DAG_) :
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ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_) {}
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virtual HazardType getHazardType(SUnit *SU, int Stalls);
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virtual void EmitInstruction(SUnit *SU);
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virtual void AdvanceCycle();
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virtual void Reset();
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};
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/// PPCHazardRecognizer970 - This class defines a finite state automata that
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/// models the dispatch logic on the PowerPC 970 (aka G5) processor. This
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/// promotes good dispatch group formation and implements noop insertion to
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/// avoid structural hazards that cause significant performance penalties (e.g.
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/// setting the CTR register then branching through it within a dispatch group),
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/// or storing then loading from the same address within a dispatch group.
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class PPCHazardRecognizer970 : public ScheduleHazardRecognizer {
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const TargetInstrInfo &TII;
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unsigned NumIssued; // Number of insts issued, including advanced cycles.
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// Various things that can cause a structural hazard.
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// HasCTRSet - If the CTR register is set in this group, disallow BCTRL.
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bool HasCTRSet;
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// StoredPtr - Keep track of the address of any store. If we see a load from
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// the same address (or one that aliases it), disallow the store. We can have
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// up to four stores in one dispatch group, hence we track up to 4.
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//
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// This is null if we haven't seen a store yet. We keep track of both
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// operands of the store here, since we support [r+r] and [r+i] addressing.
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const Value *StoreValue[4];
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int64_t StoreOffset[4];
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uint64_t StoreSize[4];
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unsigned NumStores;
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public:
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PPCHazardRecognizer970(const TargetInstrInfo &TII);
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virtual HazardType getHazardType(SUnit *SU, int Stalls);
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virtual void EmitInstruction(SUnit *SU);
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virtual void AdvanceCycle();
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virtual void Reset();
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private:
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/// EndDispatchGroup - Called when we are finishing a new dispatch group.
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///
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void EndDispatchGroup();
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/// GetInstrType - Classify the specified powerpc opcode according to its
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/// pipeline.
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PPCII::PPC970_Unit GetInstrType(unsigned Opcode,
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bool &isFirst, bool &isSingle,bool &isCracked,
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bool &isLoad, bool &isStore);
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bool isLoadOfStoredAddress(uint64_t LoadSize, int64_t LoadOffset,
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const Value *LoadValue) const;
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};
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} // end namespace llvm
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#endif
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