Dan Gohman f31408d75c Disable the register+memory forms of the bt instructions for now. Thanks ...

to Eli for pointing out that these forms don't ignore the high bits of
their index operands, and as such are not immediately suitable for use
by isel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62194 91177308-0d34-0410-b5e6-96231b3b80d8

2009-01-13 23:23:30 +00:00

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Alpha

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ARM

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CBackend

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CellSPU

Fix off-by-one error in traversing an array; this fixes a test.

2009-01-07 23:07:29 +00:00

CPP

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Generic

The list-td and list-tdrr schedulers don't yet support physreg

2009-01-13 20:24:13 +00:00

IA64

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Mips

The list-td and list-tdrr schedulers don't yet support physreg

2009-01-13 20:24:13 +00:00

PowerPC

this test should not run opt -std-compile-opts, it should run

2009-01-09 05:32:00 +00:00

SPARC

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X86

Disable the register+memory forms of the bt instructions for now. Thanks

2009-01-13 23:23:30 +00:00

XCore

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