llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-15 07:34:33 +00:00

History

Weiming Zhao fa1cf8cd68 [ARM64] Prevent bit extraction to be adjusted by following shift

For pattern like ((x >> C1) & Mask) << C2, DAG combiner may convert it
into (x >> (C1-C2)) & (Mask << C2), which makes pattern matching of ubfx
more difficult.
For example:
Given
  %shr = lshr i64 %x, 4
  %and = and i64 %shr, 15
  %arrayidx = getelementptr inbounds [8 x [64 x i64]]* @arr, i64 0, %i64 2, i64 %and
  %0 = load i64* %arrayidx
With current shift folding, it takes 3 instrs to compute base address:
  lsr x8, x0, #1
  and x8, x8, #0x78
  add x8, x9, x8

If using ubfx, it only needs 2 instrs:
  ubfx  x8, x0, #4, #4
  add x8, x9, x8, lsl #3

This fixes bug 19589


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207702 91177308-0d34-0410-b5e6-96231b3b80d8

2014-04-30 21:07:24 +00:00

AArch64

AArch64/ARM64: use HS instead of CS & LO instead of CC.

2014-04-30 13:14:03 +00:00

ARM

ARM: support stack probe emission for Windows on ARM

2014-04-30 07:05:07 +00:00

ARM64

[ARM64] Prevent bit extraction to be adjusted by following shift

2014-04-30 21:07:24 +00:00

CPP

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