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llvm-6502/test/CodeGen/ARM
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Owen Anderson 062c0a5b58 Teach DAGCombine the same multiply-by-1.0 folding trick when doing FMAs, just like it now knows for FMULs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156029 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 22:17:40 +00:00
..
2006-11-10-CycleInDAG.ll
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2007-01-19-InfiniteLoop.ll
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2007-03-07-CombinerCrash.ll
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2007-03-13-InstrSched.ll
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2007-03-21-JoinIntervalsCrash.ll
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2007-03-27-RegScavengerAssert.ll
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2007-03-30-RegScavengerAssert.ll
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2007-04-02-RegScavengerAssert.ll
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2007-04-03-PEIBug.ll
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2007-04-03-UndefinedSymbol.ll
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2007-04-30-CombinerCrash.ll
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2007-05-03-BadPostIndexedLd.ll
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2007-05-07-tailmerge-1.ll
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2007-05-09-tailmerge-2.ll
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2007-05-14-InlineAsmCstCrash.ll
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2007-05-14-RegScavengerAssert.ll
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2007-05-22-tailmerge-3.ll
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2007-05-23-BadPreIndexedStore.ll
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2007-08-15-ReuseBug.ll
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2008-02-04-LocalRegAllocBug.ll
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2008-02-29-RegAllocLocal.ll
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2008-03-05-SxtInRegBug.ll
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2008-03-07-RegScavengerAssert.ll
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2008-04-04-ScavengerAssert.ll
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2008-04-10-ScavengerAssert.ll
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2008-04-11-PHIofImpDef.ll
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2008-05-19-LiveIntervalsBug.ll
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2008-05-19-ScavengerAssert.ll
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2008-07-17-Fdiv.ll
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2008-07-24-CodeGenPrepCrash.ll
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2008-08-07-AsmPrintBug.ll
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2008-09-17-CoalescerBug.ll
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2008-11-18-ScavengerAssert.ll
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2009-02-16-SpillerBug.ll
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2009-02-22-SoftenFloatVaArg.ll
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2009-02-27-SpillerBug.ll
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2009-03-07-SpillerBug.ll
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2009-03-09-AddrModeBug.ll
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2009-04-06-AsmModifier.ll
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2009-04-08-AggregateAddr.ll
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2009-04-08-FloatUndef.ll
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2009-04-08-FREM.ll
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2009-04-09-RegScavengerAsm.ll
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2009-05-05-DAGCombineBug.ll
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2009-05-07-RegAllocLocal.ll
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2009-05-11-CodePlacementCrash.ll
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2009-05-18-InlineAsmMem.ll
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2009-06-02-ISelCrash.ll
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2009-06-04-MissingLiveIn.ll
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2009-06-15-RegScavengerAssert.ll
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2009-06-19-RegScavengerAssert.ll
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2009-06-22-CoalescerBug.ll
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2009-06-30-RegScavengerAssert2.ll
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2009-06-30-RegScavengerAssert3.ll
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2009-06-30-RegScavengerAssert4.ll
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2009-06-30-RegScavengerAssert5.ll
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2009-06-30-RegScavengerAssert.ll
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2009-07-01-CommuteBug.ll
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2009-07-09-asm-p-constraint.ll
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2009-07-18-RewriterBug.ll
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2009-07-22-ScavengerAssert.ll
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2009-07-22-SchedulerAssert.ll
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2009-07-29-VFP3Registers.ll
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2009-08-02-RegScavengerAssert-Neon.ll
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2009-08-04-RegScavengerAssert-2.ll
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2009-08-04-RegScavengerAssert.ll
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2009-08-15-RegScavenger-EarlyClobber.ll
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2009-08-15-RegScavengerAssert.ll
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2009-08-21-PostRAKill2.ll
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2009-08-21-PostRAKill3.ll
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2009-08-21-PostRAKill.ll
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2009-08-23-linkerprivate.ll
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2009-08-26-ScalarToVector.ll
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2009-08-27-ScalarToVector.ll
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2009-08-29-ExtractEltf32.ll
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2009-08-29-TooLongSplat.ll
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2009-08-31-LSDA-Name.ll
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2009-08-31-TwoRegShuffle.ll
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2009-09-09-AllOnes.ll
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2009-09-09-fpcmp-ole.ll
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2009-09-10-postdec.ll
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2009-09-13-InvalidSubreg.ll
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2009-09-13-InvalidSuperReg.ll
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2009-09-20-LiveIntervalsBug.ll
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2009-09-21-LiveVariablesBug.ll
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2009-09-22-LiveVariablesBug.ll
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2009-09-23-LiveVariablesBug.ll
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2009-09-24-spill-align.ll
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2009-09-27-CoalescerBug.ll
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2009-09-28-LdStOptiBug.ll
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2009-10-02-NEONSubregsBug.ll
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2009-10-16-Scope.ll
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2009-10-21-InvalidFNeg.ll
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2009-10-27-double-align.ll
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2009-10-30.ll
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2009-11-01-NeonMoves.ll
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2009-11-02-NegativeLane.ll
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2009-11-07-SubRegAsmPrinting.ll
Use vmov.f32 to materialize f32 consts on ARM. This relaxes constraints on
2012-03-15 18:49:02 +00:00
2009-11-13-CoalescerCrash.ll
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2009-11-13-ScavengerAssert2.ll
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2009-11-13-ScavengerAssert.ll
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2009-11-13-VRRewriterCrash.ll
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2009-11-30-LiveVariablesBug.ll
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2009-12-02-vtrn-undef.ll
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2010-03-04-eabi-fp-spill.ll
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2010-03-04-stm-undef-addr.ll
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2010-03-18-ldm-rtrn.ll
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2010-04-07-DbgValueOtherTargets.ll
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2010-04-09-NeonSelect.ll
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2010-04-13-v2f64SplitArg.ll
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2010-04-14-SplitVector.ll
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2010-04-15-ScavengerDebugValue.ll
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2010-05-14-IllegalType.ll
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2010-05-17-FastAllocCrash.ll
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2010-05-18-LocalAllocCrash.ll
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2010-05-18-PostIndexBug.ll
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2010-05-19-Shuffles.ll
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2010-05-20-NEONSpillCrash.ll
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2010-05-21-BuildVector.ll
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2010-06-11-vmovdrr-bitcast.ll
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2010-06-21-LdStMultipleBug.ll
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2010-06-21-nondarwin-tc.ll
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2010-06-25-Thumb2ITInvalidIterator.ll
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2010-06-29-PartialRedefFastAlloc.ll
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2010-06-29-SubregImpDefs.ll
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2010-07-26-GlobalMerge.ll
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2010-08-04-EHCrash.ll
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2010-08-04-StackVariable.ll
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2010-09-21-OptCmpBug.ll
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2010-09-29-mc-asm-header-test.ll
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2010-10-19-mc-elf-objheader.ll
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2010-10-25-ifcvt-ldm.ll
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2010-11-15-SpillEarlyClobber.ll
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2010-11-29-PrologueBug.ll
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2010-11-30-reloc-movt.ll
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2010-12-07-PEIBug.ll
Use vmov.f32 to materialize f32 consts on ARM. This relaxes constraints on
2012-03-15 18:49:02 +00:00
2010-12-08-tpsoft.ll
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2010-12-15-elf-lcomm.ll
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2010-12-17-LocalStackSlotCrash.ll
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2011-01-19-MergedGlobalDbg.ll
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2011-02-04-AntidepMultidef.ll
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2011-02-07-AntidepClobber.ll
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2011-03-10-DAGCombineCrash.ll
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2011-03-15-LdStMultipleBug.ll
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2011-03-23-PeepholeBug.ll
Flip the new block-placement pass to be on by default.
2012-04-16 13:49:17 +00:00
2011-04-07-schediv.ll
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2011-04-11-MachineLICMBug.ll
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2011-04-12-AlignBug.ll
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2011-04-12-FastRegAlloc.ll
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2011-04-15-AndVFlagPeepholeBug.ll
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2011-04-15-RegisterCmpPeephole.ll
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2011-04-26-SchedTweak.ll
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2011-04-27-IfCvtBug.ll
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2011-05-04-MultipleLandingPadSuccs.ll
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2011-06-09-TailCallByVal.ll
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2011-06-16-TailCallByVal.ll
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2011-06-29-MergeGlobalsAlign.ll
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2011-07-10-GlobalMergeBug.ll
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2011-08-02-MergedGlobalDbg.ll
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2011-08-12-vmovqqqq-pseudo.ll
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2011-08-25-ldmia_ret.ll
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2011-08-29-ldr_pre_imm.ll
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2011-08-29-SchedCycle.ll
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2011-09-09-OddVectorDivision.ll
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2011-09-19-cpsr.ll
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2011-09-28-CMovCombineBug.ll
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2011-10-26-ExpandUnalignedLoadCrash.ll
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2011-10-26-memset-inline.ll
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2011-10-26-memset-with-neon.ll
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2011-11-07-PromoteVectorLoadStore.ll
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2011-11-09-BitcastVectorDouble.ll
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2011-11-09-IllegalVectorFPIntConvert.ll
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2011-11-14-EarlyClobber.ll
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2011-11-28-DAGCombineBug.ll
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2011-11-29-128bitArithmetics.ll
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2011-11-30-MergeAlignment.ll
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2011-12-14-machine-sink.ll
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2011-12-19-sjlj-clobber.ll
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2012-01-23-PostRA-LICM.ll
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2012-01-24-RegSequenceLiveRange.ll
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2012-01-26-CoalescerBug.ll
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2012-01-26-CopyPropKills.ll
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2012-02-01-CoalescerBug.ll
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2012-03-05-FPSCR-bug.ll
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2012-03-13-DAGCombineBug.ll
When performing a truncating store, it's possible to rearrange the data
2012-04-09 20:32:02 +00:00
2012-03-26-FoldImmBug.ll
ARM has a peephole optimization which looks for a def / use pair. The def
2012-03-26 23:31:00 +00:00
2012-04-02-TwoAddrInstrCrash.ll
During two-address lowering, rescheduling an instruction does not untie
2012-04-02 19:58:43 +00:00
2012-04-10-DAGCombine.ll
Transform div to mul with reciprocal only when fp imm is legal.
2012-04-10 13:22:49 +00:00
2012-04-24-SplitEHCriticalEdge.ll
MachineBasicBlock::SplitCriticalEdge() should follow LLVM IR variant and refuse to break edge to EH landing pad. rdar://11300144
2012-04-24 19:06:55 +00:00
addrmode.ll
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aliases.ll
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align.ll
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alloca.ll
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argaddr.ll
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arguments2.ll
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arguments3.ll
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arguments4.ll
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arguments5.ll
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arguments6.ll
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arguments7.ll
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arguments8.ll
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arguments_f64_backfill.ll
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arguments-nosplit-double.ll
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arguments-nosplit-i64.ll
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arguments.ll
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arm-and-tst-peephole.ll
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arm-asm.ll
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arm-frameaddr.ll
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arm-modifier.ll
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arm-negative-stride.ll
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arm-returnaddr.ll
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armv4.ll
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atomic-64bit.ll
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atomic-cmp.ll
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atomic-load-store.ll
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atomic-op.ll
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available_externally.ll
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avoid-cpsr-rmw.ll
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bfc.ll
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bfi.ll
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bfx.ll
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bic.ll
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bits.ll
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bswap-inline-asm.ll
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bx_fold.ll
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call_nolink.ll
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call-tc.ll
Add proper checks.
2012-04-10 03:15:42 +00:00
call.ll
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carry.ll
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clz.ll
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code-placement.ll
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commute-movcc.ll
Pass the right sign to TLI->isLegalICmpImmediate.
2012-04-05 03:10:56 +00:00
compare-call.ll
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constants.ll
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crash-greedy-v6.ll
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crash-greedy.ll
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crash-O0.ll
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crash.ll
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cse-call.ll
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cse-libcalls.ll
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ctor_order.ll
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ctors_dtors.ll
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ctz.ll
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dagcombine-anyexttozeroext.ll
An oversight when applying the patches for r150956 and r150957 to a vanilla tree meant I forgot to svn add these testcases.
2012-04-05 10:01:12 +00:00
debug-info-arg.ll
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debug-info-blocks.ll
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debug-info-branch-folding.ll
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debug-info-d16-reg.ll
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debug-info-qreg.ll
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debug-info-s16-reg.ll
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debug-info-sreg2.ll
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div.ll
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divmod.ll
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dyn-stackalloc.ll
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eh-resume-darwin.ll
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ehabi-unwind.ll
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elf-lcomm-align.ll
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extloadi1.ll
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fabss.ll
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fadds.ll
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fast-isel-binary.ll
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fast-isel-br-const.ll
To ensure that we have more accurate line information for a block
2012-04-10 18:18:10 +00:00
fast-isel-br-phi.ll
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fast-isel-call.ll
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fast-isel-cmp-imm.ll
[fast-isel] Address Eli's comments for r152847. Specifically, add a test case
2012-03-15 22:54:20 +00:00
fast-isel-conversion.ll
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fast-isel-crash2.ll
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fast-isel-crash.ll
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fast-isel-deadcode.ll
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fast-isel-fold.ll
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fast-isel-GEP-coalesce.ll
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fast-isel-icmp.ll
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fast-isel-indirectbr.ll
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fast-isel-intrinsic.ll
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fast-isel-ldr-str-arm.ll
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fast-isel-ldr-str-thumb-neg-index.ll
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fast-isel-ldrh-strh-arm.ll
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fast-isel-mvn.ll
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fast-isel-pred.ll
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fast-isel-redefinition.ll
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fast-isel-ret.ll
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fast-isel-select.ll
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fast-isel-static.ll
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fast-isel.ll
[fast-isel] Fold "urem x, pow2" -> "and x, pow2-1". This should fix the 271%
2012-03-22 00:21:17 +00:00
fcopysign.ll
Move the constant-folding support for FP_ROUND in SelectionDAG from the one-operand version of getNode() to the two-operand version, since it became a two-operand node at sound point.
2012-04-10 22:46:53 +00:00
fdivs.ll
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fixunsdfdi.ll
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flag-crash.ll
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fmacs.ll
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fmdrr-fmrrd.ll
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fmscs.ll
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fmuls.ll
Teach DAG combine that multiplication by 1.0 can always be constant folded.
2012-05-02 21:32:35 +00:00
fnegs.ll
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fnmacs.ll
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fnmscs.ll
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fnmul.ll
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fnmuls.ll
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fold-const.ll
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formal.ll
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fp16.ll
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fp_convert.ll
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fp-arg-shuffle.ll
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fp.ll
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fparith.ll
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fpcmp_ueq.ll
ARM case-insensitive checking for APSR_nzcv.
2012-03-15 21:34:14 +00:00
fpcmp-opt.ll
ARM case-insensitive checking for APSR_nzcv.
2012-03-15 21:34:14 +00:00
fpcmp.ll
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fpconsts.ll
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fpconv.ll
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fpmem.ll
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fpow.ll
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fpowi.ll
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fptoint.ll
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fsubs.ll
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fusedMAC.ll
Teach DAGCombine the same multiply-by-1.0 folding trick when doing FMAs, just like it now knows for FMULs.
2012-05-02 22:17:40 +00:00
global-merge.ll
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globals.ll
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gv-stubs-crash.ll
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hardfloat_neon.ll
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hello.ll
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hidden-vis-2.ll
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hidden-vis-3.ll
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hidden-vis.ll
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iabs.ll
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ifcvt1.ll
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ifcvt2.ll
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ifcvt3.ll
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ifcvt4.ll
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ifcvt5.ll
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ifcvt6.ll
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ifcvt7.ll
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ifcvt8.ll
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ifcvt9.ll
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ifcvt10.ll
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ifcvt11.ll
ARM case-insensitive checking for APSR_nzcv.
2012-03-15 21:34:14 +00:00
illegal-vector-bitcast.ll
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imm.ll
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indirectbr.ll
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inlineasm2.ll
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inlineasm3.ll
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inlineasm4.ll
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inlineasm-imm-arm.ll
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inlineasm.ll
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insn-sched1.ll
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int-to-fp.ll
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intrinsics.ll
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ispositive.ll
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jumptable-label.ll
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large-stack.ll
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ldm.ll
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ldr_ext.ll
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ldr_frame.ll
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ldr_post.ll
FileCheckize these tests.
2012-04-16 20:56:42 +00:00
ldr_pre.ll
FileCheckize these tests.
2012-04-16 20:56:42 +00:00
ldr.ll
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ldrd-memoper.ll
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ldrd.ll
Implement a bastardized ABI.
2012-04-27 02:11:10 +00:00
ldst-f32-2-i32.ll
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ldstrexd.ll
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lit.local.cfg
Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu
2012-03-25 09:02:19 +00:00
load_i1_select.ll
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load-global.ll
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load.ll
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log2_not_readnone.ll
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long_shift.ll
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long-setcc.ll
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long.ll
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lsr-code-insertion.ll
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lsr-icmp-imm.ll
Allow negative immediates in ARM and Thumb2 compares.
2012-04-06 17:45:04 +00:00
lsr-scale-addr-mode.ll
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lsr-unfolded-offset.ll
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machine-cse-cmp.ll
Implement ARMBaseInstrInfo::commuteInstruction() for MOVCCr.
2012-04-04 18:23:42 +00:00
machine-licm.ll
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mem.ll
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memcpy-inline.ll
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memfunc.ll
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mls.ll
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movt-movw-global.ll
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movt.ll
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mul_const.ll
Perform mul combine when multiplying wiht negative constants.
2012-03-19 19:19:50 +00:00
mul.ll
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mulhi.ll
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mult-alt-generic-arm.ll
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mvn.ll
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neon_arith1.ll
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neon_div.ll
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neon_ld1.ll
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neon_ld2.ll
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neon_minmax.ll
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neon_shift.ll
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neon_spill.ll
Add <imp-def> operands when reloading into physregs.
2012-03-06 02:48:17 +00:00
odr_comdat.ll
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opt-shuff-tstore.ll
When performing a truncating store, it's possible to rearrange the data
2012-04-09 20:32:02 +00:00
pack.ll
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peephole-bitcast.ll
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phi.ll
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pr3502.ll
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prefetch.ll
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private.ll
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reg_asc_order.ll
Allocate virtual registers in ascending order.
2012-04-02 22:30:39 +00:00
reg_sequence.ll
This commit contains a few changes that had to go in together.
2012-04-01 19:31:22 +00:00
ret0.ll
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ret_arg1.ll
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ret_arg2.ll
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ret_arg3.ll
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ret_arg4.ll
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ret_arg5.ll
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ret_f32_arg2.ll
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ret_f32_arg5.ll
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ret_f64_arg2.ll
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ret_f64_arg_reg_split.ll
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ret_f64_arg_split.ll
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ret_f64_arg_stack.ll
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ret_i64_arg2.ll
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ret_i64_arg3.ll
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ret_i64_arg_split.ll
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ret_i128_arg2.ll
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ret_void.ll
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rev.ll
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sbfx.ll
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section.ll
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select_xform.ll
Fix test case from r153135.
2012-03-20 21:49:54 +00:00
select-imm.ll
Implement ARMBaseInstrInfo::commuteInstruction() for MOVCCr.
2012-04-04 18:23:42 +00:00
select.ll
Allocate virtual registers in ascending order.
2012-04-02 22:30:39 +00:00
shifter_operand.ll
Extend r148086 to check for [r +/- reg] address mode. This fixes queens performance regression (due to increased register pressure from overly aggressive pre-inc formation).
2012-03-06 23:33:32 +00:00
shuffle.ll
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smul.ll
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spill-q.ll
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stack-frame.ll
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stm.ll
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str_post.ll
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str_pre-2.ll
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str_pre.ll
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str_trunc.ll
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sub.ll
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subreg-remat.ll
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sxt_rot.ll
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t2-imm.ll
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tail-dup.ll
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tail-opts.ll
Flip the new block-placement pass to be on by default.
2012-04-16 13:49:17 +00:00
test-sharedidx.ll
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thread_pointer.ll
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thumb1-varalloc.ll
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thumb2-it-block.ll
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tls1.ll
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tls2.ll
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tls3.ll
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trap.ll
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trunc_ldr.ll
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truncstore-dag-combine.ll
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tst_teq.ll
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uint64tof64.ll
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umulo-32.ll
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unaligned_load_store.ll
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undef-sext.ll
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unord.ll
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uxt_rot.ll
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uxtb.ll
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va_arg.ll
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vaba.ll
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vabd.ll
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vabs.ll
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vadd.ll
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vargs_align.ll
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vargs.ll
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vbits.ll
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vbsl-constant.ll
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vbsl.ll
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vceq.ll
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vcge.ll
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vcgt.ll
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vcnt.ll
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vcombine.ll
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vcvt_combine.ll
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vcvt.ll
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vdiv_combine.ll
Convert floating point division by a constant into multiplication by the
2012-04-07 20:04:00 +00:00
vdup.ll
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vector-DAGCombine.ll
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vector-extend-narrow.ll
Use VLD1 in NEON extenting-load patterns instead of VLDR.
2012-04-26 08:46:29 +00:00
vext.ll
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vfcmp.ll
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vfp.ll
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vget_lane.ll
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vhadd.ll
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vhsub.ll
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vicmp.ll
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vld1.ll
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vld2.ll
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vld3.ll
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vld4.ll
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vlddup.ll
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vldlane.ll
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vminmax.ll
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vmla.ll
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vmls.ll
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vmov.ll
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vmul.ll
Don't introduce illegal types when creating vmull operations. <rdar://11324364>
2012-04-30 16:53:34 +00:00
vneg.ll
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vpadal.ll
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vpadd.ll
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vpminmax.ll
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vqadd.ll
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vqdmul.ll
…
vqshl.ll
…
vqshrn.ll
…
vqsub.ll
…
vrec.ll
…
vrev.ll
When performing a truncating store, it's possible to rearrange the data
2012-04-09 20:32:02 +00:00
vshift.ll
…
vshiftins.ll
…
vshl.ll
…
vshll.ll
…
vshrn.ll
…
vsra.ll
…
vst1.ll
…
vst2.ll
…
vst3.ll
…
vst4.ll
…
vstlane.ll
…
vsub.ll
…
vtbl.ll
…
vtrn.ll
…
vuzp.ll
…
vzip.ll
…
weak2.ll
…
weak.ll
…
widen-vmovs.ll
Disable code placement for this test.
2012-04-16 20:49:06 +00:00