6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-09 13:33:17 +00:00
Code Issues Projects Releases Wiki Activity
llvm-6502/lib/Target
History
Chris Lattner f3bf50d2c8 Add empty patterns for F3_2 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24771 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-17 08:06:43 +00:00
..
Alpha
fix FP selects
2005-12-12 20:30:09 +00:00
CBackend
do not allow '.' in symbol names
2005-11-10 21:39:29 +00:00
IA64
Add some explicit type casts so that tblgen knows the type of the shiftamount, which is not necessarily the same as the type being shifted.
2005-12-05 02:34:29 +00:00
PowerPC
Added source file/line correspondence for dwarf (PowerPC only at this point.)
2005-12-16 22:45:29 +00:00
Skeleton
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
2005-12-01 04:51:06 +00:00
Sparc
Add empty patterns for F3_2 instructions
2005-12-17 08:06:43 +00:00
SparcV8
Add empty patterns for F3_2 instructions
2005-12-17 08:06:43 +00:00
SparcV9
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
2005-12-01 04:51:06 +00:00
X86
Remove a few lines of dead code.
2005-12-17 07:18:44 +00:00
Makefile
DONT_BUILD_RELINKED is gone and implied by BUILD_ARCHIVE now
2005-10-24 02:26:13 +00:00
MRegisterInfo.cpp
Rename MRegisterDesc -> TargetRegisterDesc for consistency
2005-09-30 17:49:27 +00:00
SubtargetFeature.cpp
Preparation of supporting scheduling info. Need to find info based on selected
2005-10-25 15:15:28 +00:00
Target.td
Added support to specify predicates.
2005-12-14 22:02:59 +00:00
TargetData.cpp
…
TargetFrameInfo.cpp
…
TargetInstrInfo.cpp
…
TargetMachine.cpp
…
TargetMachineRegistry.cpp
…
TargetSchedInfo.cpp
…
TargetSchedule.td
add a marker
2005-10-23 22:07:20 +00:00
TargetSelectionDAG.td
Added source file/line correspondence for dwarf (PowerPC only at this point.)
2005-12-16 22:45:29 +00:00
TargetSubtarget.cpp
…