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f4a4e3ae740979ea7877f55e34cdb5abac9cbe33
llvm-6502/test/MC
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Craig Topper 566f233ba6 Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15 20:46:47 +00:00
..
ARM
Update test for disabling of code/data marker labels in ELF.
2011-10-14 21:12:55 +00:00
AsmParser
Added regression test for bug #10869.
2011-09-19 07:48:08 +00:00
COFF
…
Disassembler
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
2011-10-15 20:46:47 +00:00
ELF
Apparently, sometimes llvm-nm doesn't put the undefined symbol at the top. Take
2011-10-11 06:58:11 +00:00
MachO
Fix a Darwin x86_64 special case of a jmp to a temporary symbol from an atom
2011-09-08 20:53:44 +00:00
MBlaze
…
X86
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
2011-10-15 20:46:47 +00:00
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