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https://github.com/c64scene-ar/llvm-6502.git
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97f4d01ee1
Summary: CUDA 7.0's libdevice uses slightly different IR to call __nvvm_reflect and that triggers an assertion in nvvm_reflect optimization pass. This change allows nvvm_reflect pass to deal with both old and new ways to pass an argument to __nvvm_reflect. Test Plan: ninja check-all Reviewers: eliben, echristo Subscribers: jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D8399 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232732 91177308-0d34-0410-b5e6-96231b3b80d8
80 lines
2.6 KiB
LLVM
80 lines
2.6 KiB
LLVM
; RUN: opt < %s -S -nvvm-reflect -nvvm-reflect-list USE_MUL=0 -O2 | FileCheck %s --check-prefix=USE_MUL_0
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; RUN: opt < %s -S -nvvm-reflect -nvvm-reflect-list USE_MUL=1 -O2 | FileCheck %s --check-prefix=USE_MUL_1
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@str = private unnamed_addr addrspace(4) constant [8 x i8] c"USE_MUL\00"
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declare i32 @__nvvm_reflect(i8*)
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declare i8* @llvm.nvvm.ptr.constant.to.gen.p0i8.p4i8(i8 addrspace(4)*)
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define float @foo(float %a, float %b) {
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; USE_MUL_0: define float @foo
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; USE_MUL_0-NOT: call i32 @__nvvm_reflect
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; USE_MUL_1: define float @foo
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; USE_MUL_1-NOT: call i32 @__nvvm_reflect
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%ptr = tail call i8* @llvm.nvvm.ptr.constant.to.gen.p0i8.p4i8(i8 addrspace(4)* getelementptr inbounds ([8 x i8], [8 x i8] addrspace(4)* @str, i32 0, i32 0))
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%reflect = tail call i32 @__nvvm_reflect(i8* %ptr)
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%cmp = icmp ugt i32 %reflect, 0
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br i1 %cmp, label %use_mul, label %use_add
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use_mul:
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; USE_MUL_1: fmul float %a, %b
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; USE_MUL_0-NOT: fadd float %a, %b
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%ret1 = fmul float %a, %b
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br label %exit
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use_add:
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; USE_MUL_0: fadd float %a, %b
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; USE_MUL_1-NOT: fmul float %a, %b
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%ret2 = fadd float %a, %b
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br label %exit
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exit:
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%ret = phi float [%ret1, %use_mul], [%ret2, %use_add]
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ret float %ret
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}
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declare i32 @llvm.nvvm.reflect.p0i8(i8*)
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; USE_MUL_0: define i32 @intrinsic
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; USE_MUL_1: define i32 @intrinsic
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define i32 @intrinsic() {
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; USE_MUL_0-NOT: call i32 @llvm.nvvm.reflect
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; USE_MUL_0: ret i32 0
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; USE_MUL_1-NOT: call i32 @llvm.nvvm.reflect
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; USE_MUL_1: ret i32 1
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%ptr = tail call i8* @llvm.nvvm.ptr.constant.to.gen.p0i8.p4i8(i8 addrspace(4)* getelementptr inbounds ([8 x i8], [8 x i8] addrspace(4)* @str, i32 0, i32 0))
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%reflect = tail call i32 @llvm.nvvm.reflect.p0i8(i8* %ptr)
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ret i32 %reflect
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}
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; CUDA-7.0 passes __nvvm_reflect argument slightly differently.
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; Verify that it works, too
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@"$str" = private addrspace(1) constant [8 x i8] c"USE_MUL\00"
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define float @bar(float %a, float %b) {
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; USE_MUL_0: define float @bar
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; USE_MUL_0-NOT: call i32 @__nvvm_reflect
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; USE_MUL_1: define float @bar
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; USE_MUL_1-NOT: call i32 @__nvvm_reflect
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%reflect = call i32 @__nvvm_reflect(i8* addrspacecast (i8 addrspace(1)* getelementptr inbounds ([8 x i8], [8 x i8] addrspace(1)* @"$str", i32 0, i32 0) to i8*))
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%cmp = icmp ne i32 %reflect, 0
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br i1 %cmp, label %use_mul, label %use_add
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use_mul:
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; USE_MUL_1: fmul float %a, %b
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; USE_MUL_0-NOT: fadd float %a, %b
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%ret1 = fmul float %a, %b
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br label %exit
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use_add:
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; USE_MUL_0: fadd float %a, %b
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; USE_MUL_1-NOT: fmul float %a, %b
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%ret2 = fadd float %a, %b
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br label %exit
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exit:
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%ret = phi float [%ret1, %use_mul], [%ret2, %use_add]
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ret float %ret
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}
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