Tim Northover f635ab8eab ARM: permit bare dmb/dsb/isb aliases on Cortex-M0 ... Cortex-M0 supports these 32-bit instructions despite being Thumb1 only (mostly). We knew about that but not that the aliases without the default "sy" operand were also permitted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194094 91177308-0d34-0410-b5e6-96231b3b80d8		2013-11-05 21:36:02 +00:00
..
AArch64	Implement AArch64 Neon Crypto instruction classes AES, SHA, and 3 SHA.	2013-11-05 17:42:05 +00:00
ARM	ARM: permit bare dmb/dsb/isb aliases on Cortex-M0	2013-11-05 21:36:02 +00:00
AsmParser	MCParser/Debug info: Accept line number 0 as a legitimate value, since	2013-09-26 23:37:11 +00:00
COFF	MC asm parser: allow ?'s in symbol names, and handle @'s in names in MS asm	2013-10-18 20:46:28 +00:00
Disassembler	Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post).	2013-11-05 03:39:32 +00:00
ELF	This commit adds some (but not all) of the x86-64 relocations that are not	2013-10-30 18:47:25 +00:00
MachO	Add test I forgot to git add in r191824.	2013-10-02 14:49:41 +00:00
Markup
Mips	Support for microMIPS branch instructions.	2013-11-04 14:53:22 +00:00
PowerPC	Convert another llc -filetype=obj test.	2013-10-28 22:17:19 +00:00
SystemZ	[SystemZ] Add comparisons of high words and memory	2013-10-01 15:00:44 +00:00
X86	Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions.	2013-10-14 04:55:01 +00:00