Tanya Lattner db40cf1b58 Added new circuit finding alogrithm. ...

Fixed bug in graph so that phi ite diff edges are added.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20108 91177308-0d34-0410-b5e6-96231b3b80d8

2005-02-10 17:02:58 +00:00

..

Alpha

so, if you beat on it, you too can talk emacs into having a sane indenting policy... Also, optimize many function calls with pc-relative calls (partial prologue skipping for that case coming soon), try to fix the random jumps to strange places problem by pesimizing div et. al. register usage and fixing up GP before using, some calling convention tweaks, and make frame pointer unallocatable (not strickly necessary, but let's go for correctness first)

2005-02-10 06:25:22 +00:00

CBackend

Fix hyphenation in output comment

2005-01-31 06:19:57 +00:00

PowerPC

Fix Regression/CodeGen/PowerPC/2005-01-14-UndefLong.ll

2005-01-14 20:22:02 +00:00

Skeleton

ignore generated files

2004-11-21 00:01:54 +00:00

Sparc

Substantially improve the code generated by non-folded setcc instructions.

2005-01-01 16:06:57 +00:00

SparcV8

Substantially improve the code generated by non-folded setcc instructions.

2005-01-01 16:06:57 +00:00

SparcV9

Added new circuit finding alogrithm.

2005-02-10 17:02:58 +00:00

X86

We can fold promoted and non-promoted loads into divs also!

2005-01-25 20:35:10 +00:00

Makefile

Build Alpha by default.

2005-01-23 04:34:46 +00:00

MRegisterInfo.cpp

…

Target.td

Add some bits that can be set for instructions.

2005-01-02 02:27:48 +00:00

TargetData.cpp

Initial support for packed types, contributed by Morten Ofstad

2004-12-01 17:14:28 +00:00

TargetFrameInfo.cpp

…

TargetInstrInfo.cpp

Finegrainify namespacification

2005-01-19 06:53:34 +00:00

TargetMachine.cpp

Add a new target-independent code generator flag.

2005-01-15 06:00:32 +00:00

TargetMachineRegistry.cpp

…

TargetSchedInfo.cpp

Improve compatiblity with HPUX on Itanium, patch by Duraid Madina

2005-01-16 01:31:31 +00:00