llvm-6502/lib/Target/Mos6502/Mos6502InstrInfo.cpp
2015-08-03 20:10:07 -03:00

455 lines
16 KiB
C++

//===-- Mos6502InstrInfo.cpp - Mos6502 Instruction Information ----------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the Mos6502 implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//
#include "Mos6502InstrInfo.h"
#include "Mos6502.h"
#include "Mos6502MachineFunctionInfo.h"
#include "Mos6502Subtarget.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
#define GET_INSTRINFO_CTOR_DTOR
#include "Mos6502GenInstrInfo.inc"
// Pin the vtable to this file.
void Mos6502InstrInfo::anchor() {}
Mos6502InstrInfo::Mos6502InstrInfo(Mos6502Subtarget &ST)
: Mos6502GenInstrInfo(M6502::ADJCALLSTACKDOWN, M6502::ADJCALLSTACKUP), RI(),
Subtarget(ST) {}
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than loading from the stack slot.
unsigned Mos6502InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const {
if (MI->getOpcode() == M6502::LDri ||
MI->getOpcode() == M6502::LDXri ||
MI->getOpcode() == M6502::LDFri ||
MI->getOpcode() == M6502::LDDFri ||
MI->getOpcode() == M6502::LDQFri) {
if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
}
return 0;
}
/// isStoreToStackSlot - If the specified machine instruction is a direct
/// store to a stack slot, return the virtual or physical register number of
/// the source reg along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than storing to the stack slot.
unsigned Mos6502InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
int &FrameIndex) const {
if (MI->getOpcode() == M6502::STri ||
MI->getOpcode() == M6502::STXri ||
MI->getOpcode() == M6502::STFri ||
MI->getOpcode() == M6502::STDFri ||
MI->getOpcode() == M6502::STQFri) {
if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
MI->getOperand(1).getImm() == 0) {
FrameIndex = MI->getOperand(0).getIndex();
return MI->getOperand(2).getReg();
}
}
return 0;
}
static bool IsIntegerCC(unsigned CC)
{
return (CC <= SPCC::ICC_VC);
}
static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
{
switch(CC) {
case SPCC::ICC_A: return SPCC::ICC_N;
case SPCC::ICC_N: return SPCC::ICC_A;
case SPCC::ICC_NE: return SPCC::ICC_E;
case SPCC::ICC_E: return SPCC::ICC_NE;
case SPCC::ICC_G: return SPCC::ICC_LE;
case SPCC::ICC_LE: return SPCC::ICC_G;
case SPCC::ICC_GE: return SPCC::ICC_L;
case SPCC::ICC_L: return SPCC::ICC_GE;
case SPCC::ICC_GU: return SPCC::ICC_LEU;
case SPCC::ICC_LEU: return SPCC::ICC_GU;
case SPCC::ICC_CC: return SPCC::ICC_CS;
case SPCC::ICC_CS: return SPCC::ICC_CC;
case SPCC::ICC_POS: return SPCC::ICC_NEG;
case SPCC::ICC_NEG: return SPCC::ICC_POS;
case SPCC::ICC_VC: return SPCC::ICC_VS;
case SPCC::ICC_VS: return SPCC::ICC_VC;
case SPCC::FCC_A: return SPCC::FCC_N;
case SPCC::FCC_N: return SPCC::FCC_A;
case SPCC::FCC_U: return SPCC::FCC_O;
case SPCC::FCC_O: return SPCC::FCC_U;
case SPCC::FCC_G: return SPCC::FCC_ULE;
case SPCC::FCC_LE: return SPCC::FCC_UG;
case SPCC::FCC_UG: return SPCC::FCC_LE;
case SPCC::FCC_ULE: return SPCC::FCC_G;
case SPCC::FCC_L: return SPCC::FCC_UGE;
case SPCC::FCC_GE: return SPCC::FCC_UL;
case SPCC::FCC_UL: return SPCC::FCC_GE;
case SPCC::FCC_UGE: return SPCC::FCC_L;
case SPCC::FCC_LG: return SPCC::FCC_UE;
case SPCC::FCC_UE: return SPCC::FCC_LG;
case SPCC::FCC_NE: return SPCC::FCC_E;
case SPCC::FCC_E: return SPCC::FCC_NE;
}
llvm_unreachable("Invalid cond code");
}
bool Mos6502InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const
{
MachineBasicBlock::iterator I = MBB.end();
MachineBasicBlock::iterator UnCondBrIter = MBB.end();
while (I != MBB.begin()) {
--I;
if (I->isDebugValue())
continue;
// When we see a non-terminator, we are done.
if (!isUnpredicatedTerminator(I))
break;
// Terminator is not a branch.
if (!I->isBranch())
return true;
// Handle Unconditional branches.
if (I->getOpcode() == M6502::BA) {
UnCondBrIter = I;
if (!AllowModify) {
TBB = I->getOperand(0).getMBB();
continue;
}
while (std::next(I) != MBB.end())
std::next(I)->eraseFromParent();
Cond.clear();
FBB = nullptr;
if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
TBB = nullptr;
I->eraseFromParent();
I = MBB.end();
UnCondBrIter = MBB.end();
continue;
}
TBB = I->getOperand(0).getMBB();
continue;
}
unsigned Opcode = I->getOpcode();
if (Opcode != M6502::BCOND && Opcode != M6502::FBCOND)
return true; // Unknown Opcode.
SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm();
if (Cond.empty()) {
MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
if (AllowModify && UnCondBrIter != MBB.end() &&
MBB.isLayoutSuccessor(TargetBB)) {
// Transform the code
//
// brCC L1
// ba L2
// L1:
// ..
// L2:
//
// into
//
// brnCC L2
// L1:
// ...
// L2:
//
BranchCode = GetOppositeBranchCondition(BranchCode);
MachineBasicBlock::iterator OldInst = I;
BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
.addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode);
BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(M6502::BA))
.addMBB(TargetBB);
OldInst->eraseFromParent();
UnCondBrIter->eraseFromParent();
UnCondBrIter = MBB.end();
I = MBB.end();
continue;
}
FBB = TBB;
TBB = I->getOperand(0).getMBB();
Cond.push_back(MachineOperand::CreateImm(BranchCode));
continue;
}
// FIXME: Handle subsequent conditional branches.
// For now, we can't handle multiple conditional branches.
return true;
}
return false;
}
unsigned
Mos6502InstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
DebugLoc DL) const {
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 1 || Cond.size() == 0) &&
"Mos6502 branch conditions should have one component!");
if (Cond.empty()) {
assert(!FBB && "Unconditional branch with multiple successors!");
BuildMI(&MBB, DL, get(M6502::BA)).addMBB(TBB);
return 1;
}
// Conditional branch
unsigned CC = Cond[0].getImm();
if (IsIntegerCC(CC))
BuildMI(&MBB, DL, get(M6502::BCOND)).addMBB(TBB).addImm(CC);
else
BuildMI(&MBB, DL, get(M6502::FBCOND)).addMBB(TBB).addImm(CC);
if (!FBB)
return 1;
BuildMI(&MBB, DL, get(M6502::BA)).addMBB(FBB);
return 2;
}
unsigned Mos6502InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const
{
MachineBasicBlock::iterator I = MBB.end();
unsigned Count = 0;
while (I != MBB.begin()) {
--I;
if (I->isDebugValue())
continue;
if (I->getOpcode() != M6502::BA
&& I->getOpcode() != M6502::BCOND
&& I->getOpcode() != M6502::FBCOND)
break; // Not a branch
I->eraseFromParent();
I = MBB.end();
++Count;
}
return Count;
}
void Mos6502InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const {
unsigned numSubRegs = 0;
unsigned movOpc = 0;
const unsigned *subRegIdx = nullptr;
const unsigned DFP_FP_SubRegsIdx[] = { M6502::sub_even, M6502::sub_odd };
const unsigned QFP_DFP_SubRegsIdx[] = { M6502::sub_even64, M6502::sub_odd64 };
const unsigned QFP_FP_SubRegsIdx[] = { M6502::sub_even, M6502::sub_odd,
M6502::sub_odd64_then_sub_even,
M6502::sub_odd64_then_sub_odd };
if (M6502::IntRegsRegClass.contains(DestReg, SrcReg))
BuildMI(MBB, I, DL, get(M6502::ORrr), DestReg).addReg(M6502::G0)
.addReg(SrcReg, getKillRegState(KillSrc));
else if (M6502::FPRegsRegClass.contains(DestReg, SrcReg))
BuildMI(MBB, I, DL, get(M6502::FMOVS), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc));
else if (M6502::DFPRegsRegClass.contains(DestReg, SrcReg)) {
if (Subtarget.isV9()) {
BuildMI(MBB, I, DL, get(M6502::FMOVD), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc));
} else {
// Use two FMOVS instructions.
subRegIdx = DFP_FP_SubRegsIdx;
numSubRegs = 2;
movOpc = M6502::FMOVS;
}
} else if (M6502::QFPRegsRegClass.contains(DestReg, SrcReg)) {
if (Subtarget.isV9()) {
if (Subtarget.hasHardQuad()) {
BuildMI(MBB, I, DL, get(M6502::FMOVQ), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc));
} else {
// Use two FMOVD instructions.
subRegIdx = QFP_DFP_SubRegsIdx;
numSubRegs = 2;
movOpc = M6502::FMOVD;
}
} else {
// Use four FMOVS instructions.
subRegIdx = QFP_FP_SubRegsIdx;
numSubRegs = 4;
movOpc = M6502::FMOVS;
}
} else if (M6502::ASRRegsRegClass.contains(DestReg) &&
M6502::IntRegsRegClass.contains(SrcReg)) {
BuildMI(MBB, I, DL, get(M6502::WRASRrr), DestReg)
.addReg(M6502::G0)
.addReg(SrcReg, getKillRegState(KillSrc));
} else if (M6502::IntRegsRegClass.contains(DestReg) &&
M6502::ASRRegsRegClass.contains(SrcReg)) {
BuildMI(MBB, I, DL, get(M6502::RDASR), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc));
} else
llvm_unreachable("Impossible reg-to-reg copy");
if (numSubRegs == 0 || subRegIdx == nullptr || movOpc == 0)
return;
const TargetRegisterInfo *TRI = &getRegisterInfo();
MachineInstr *MovMI = nullptr;
for (unsigned i = 0; i != numSubRegs; ++i) {
unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]);
unsigned Src = TRI->getSubReg(SrcReg, subRegIdx[i]);
assert(Dst && Src && "Bad sub-register");
MovMI = BuildMI(MBB, I, DL, get(movOpc), Dst).addReg(Src);
}
// Add implicit super-register defs and kills to the last MovMI.
MovMI->addRegisterDefined(DestReg, TRI);
if (KillSrc)
MovMI->addRegisterKilled(SrcReg, TRI);
}
void Mos6502InstrInfo::
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
DebugLoc DL;
if (I != MBB.end()) DL = I->getDebugLoc();
MachineFunction *MF = MBB.getParent();
const MachineFrameInfo &MFI = *MF->getFrameInfo();
MachineMemOperand *MMO =
MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
MachineMemOperand::MOStore,
MFI.getObjectSize(FI),
MFI.getObjectAlignment(FI));
// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
if (RC == &M6502::I64RegsRegClass)
BuildMI(MBB, I, DL, get(M6502::STXri)).addFrameIndex(FI).addImm(0)
.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
else if (RC == &M6502::IntRegsRegClass)
BuildMI(MBB, I, DL, get(M6502::STri)).addFrameIndex(FI).addImm(0)
.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
else if (RC == &M6502::FPRegsRegClass)
BuildMI(MBB, I, DL, get(M6502::STFri)).addFrameIndex(FI).addImm(0)
.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
else if (M6502::DFPRegsRegClass.hasSubClassEq(RC))
BuildMI(MBB, I, DL, get(M6502::STDFri)).addFrameIndex(FI).addImm(0)
.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
else if (M6502::QFPRegsRegClass.hasSubClassEq(RC))
// Use STQFri irrespective of its legality. If STQ is not legal, it will be
// lowered into two STDs in eliminateFrameIndex.
BuildMI(MBB, I, DL, get(M6502::STQFri)).addFrameIndex(FI).addImm(0)
.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
else
llvm_unreachable("Can't store this register to stack slot");
}
void Mos6502InstrInfo::
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned DestReg, int FI,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
DebugLoc DL;
if (I != MBB.end()) DL = I->getDebugLoc();
MachineFunction *MF = MBB.getParent();
const MachineFrameInfo &MFI = *MF->getFrameInfo();
MachineMemOperand *MMO =
MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
MachineMemOperand::MOLoad,
MFI.getObjectSize(FI),
MFI.getObjectAlignment(FI));
if (RC == &M6502::I64RegsRegClass)
BuildMI(MBB, I, DL, get(M6502::LDXri), DestReg).addFrameIndex(FI).addImm(0)
.addMemOperand(MMO);
else if (RC == &M6502::IntRegsRegClass)
BuildMI(MBB, I, DL, get(M6502::LDri), DestReg).addFrameIndex(FI).addImm(0)
.addMemOperand(MMO);
else if (RC == &M6502::FPRegsRegClass)
BuildMI(MBB, I, DL, get(M6502::LDFri), DestReg).addFrameIndex(FI).addImm(0)
.addMemOperand(MMO);
else if (M6502::DFPRegsRegClass.hasSubClassEq(RC))
BuildMI(MBB, I, DL, get(M6502::LDDFri), DestReg).addFrameIndex(FI).addImm(0)
.addMemOperand(MMO);
else if (M6502::QFPRegsRegClass.hasSubClassEq(RC))
// Use LDQFri irrespective of its legality. If LDQ is not legal, it will be
// lowered into two LDDs in eliminateFrameIndex.
BuildMI(MBB, I, DL, get(M6502::LDQFri), DestReg).addFrameIndex(FI).addImm(0)
.addMemOperand(MMO);
else
llvm_unreachable("Can't load this register from stack slot");
}
unsigned Mos6502InstrInfo::getGlobalBaseReg(MachineFunction *MF) const
{
Mos6502MachineFunctionInfo *Mos6502FI = MF->getInfo<Mos6502MachineFunctionInfo>();
unsigned GlobalBaseReg = Mos6502FI->getGlobalBaseReg();
if (GlobalBaseReg != 0)
return GlobalBaseReg;
// Insert the set of GlobalBaseReg into the first MBB of the function
MachineBasicBlock &FirstMBB = MF->front();
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
MachineRegisterInfo &RegInfo = MF->getRegInfo();
const TargetRegisterClass *PtrRC =
Subtarget.is64Bit() ? &M6502::I64RegsRegClass : &M6502::IntRegsRegClass;
GlobalBaseReg = RegInfo.createVirtualRegister(PtrRC);
DebugLoc dl;
BuildMI(FirstMBB, MBBI, dl, get(M6502::GETPCX), GlobalBaseReg);
Mos6502FI->setGlobalBaseReg(GlobalBaseReg);
return GlobalBaseReg;
}