Bradley Smith f797751ca0 [ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205882 91177308-0d34-0410-b5e6-96231b3b80d8		2014-04-09 14:43:35 +00:00
..
AArch64
ARM
ARM64	[ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0.	2014-04-09 14:43:35 +00:00
Mips	This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well.	2014-03-03 13:12:59 +00:00
PowerPC	[PowerPC] Initial support for the VSX instruction set	2014-03-13 07:58:58 +00:00
Sparc	[Sparc] Add support for decoding 'swap' instruction.	2014-03-09 23:32:07 +00:00
SystemZ	[SystemZ] Add support for z196 float<->unsigned conversions	2014-03-21 10:56:30 +00:00
X86	Test case for r204305.	2014-03-20 06:45:10 +00:00
XCore