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dfca6eec31
This is being disabled because it is no longer needed for performance. It is only used by postRAscheduler which is also planned for removal, and it is implemented with an out-dated view of register liveness. It consideres aliases instead of register units, assumes valid kill flags, and assumes implicit uses on partial register defs. Kill flags and implicit operands are error prone and impossible to verify. We should gradually eliminate dependence on them in the postRA phases. Targets that still benefit from this should move to the MI scheduler. If that doesn't solve the problem, then we should add a hook to regalloc to optimize reload placement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191348 91177308-0d34-0410-b5e6-96231b3b80d8
22 lines
834 B
LLVM
22 lines
834 B
LLVM
; Make sure short memsets on ARM lower to stores, even when optimizing for size.
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; RUN: llc -march=arm < %s | FileCheck %s -check-prefix=CHECK-GENERIC
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; RUN: llc -march=arm -mcpu=cortex-a8 < %s | FileCheck %s -check-prefix=CHECK-UNALIGNED
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target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
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target triple = "thumbv7-apple-ios5.0.0"
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; CHECK-GENERIC: strb
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; CHECK-GENERIT-NEXT: strb
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; CHECK-GENERIT-NEXT: strb
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; CHECK-GENERIT-NEXT: strb
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; CHECK-GENERIT-NEXT: strb
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; CHECK-UNALIGNED: strb
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; CHECK-UNALIGNED: str
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define void @foo(i8* nocapture %c) nounwind optsize {
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entry:
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call void @llvm.memset.p0i8.i64(i8* %c, i8 -1, i64 5, i32 1, i1 false)
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ret void
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}
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declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
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